IPC and CEERIS DPMO Methodologies Compatible

CEERIS pioneered the use of DPMO (defects per million opportunities) as a unique tool to measure printed circuit board assembly process performances and to implement improvements. At the root of the methodology is the count of opportunities for defects (OFDs). For the last decade, CEERIS has defined OFD as the sum of the number of parts and the number of solder joints. The recently published IPC methodology defines OFDs as number of components plus number of parts plus number of solder joints. In fact, this difference in methodology does not affect DPMO benchmarking values previously published by CEERIS (http://www.ceeris.com/DPMO.htm).

The reason CEERIS only counts number of parts and number of solder joints is because it analyzes the PROCESS performances. Adding the number of components to the OFD count is justified when the DPMO analysis also covers component failures. CEERIS takes great care to NOT include defective components identified during the assembly and test into its computation of the process DPMO. By example, the electronic failure of a component is excluded from the CEERIS defect count while an error in test software is a true process defect.

For future DPMO benchmarking research, CEERIS shall adopt the IPC counting method for OFDs. This will not impact the validity of the statistical series previously published by CEERIS in various reports. It will simply allow CEERIS to cover both the material as well as the process quality performances.

If you wish your facility to be part of future DPMO programs sponsored by CEERIS, please contact us at ceeris@aol.com