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International Wafer-Level Packaging Conference (IWLPC) Keynote Presenters Announced

Jun 19, 2016

The SMTA and Chip Scale Review magazine are pleased to announce the Keynote Presenters for the 13th Annual International Wafer-Level Packaging Conference. The IWLPC will be held October 18-20, 2016 at the DoubleTree Airport Hotel in San Jose, California.

Klaus-Dieter Lang, Ph.D., Fraunhofer IZM is scheduled to give the keynote presentation on the first day of the conference on “Advanced Technology Platforms for Next Generation of Smart Systems.” The trend to establish smart electronic systems in an increasing number of application fields (e.g., Internet of Things) is enormous. But because of huge product variation, the main precondition to manufacture such systems is complex design tools, standardized leading edge processes, and system oriented test procedures. The allocation of innovative technology platforms (e.g., advanced assembly and packaging) and extended test principles (e.g., technology and functionality) are needed to achieve high yields and reasonable costs. Presentation topics include application conditions, integration technologies and reliability aspects for smart electronic systems. Examples from wearables, communication and production illustrate the advantage of their use.

Prof. Lang studied Electrical Engineering and received his M.S. Equivalent Diploma (Metallization Layers on GaAs). In 1985, he received his Ph.D. and in 1989 he received his Doctor of Technical Science. In 1993, he became Section Manager for Chip Interconnections at Fraunhofer IZM and from 2003 he headed the Department "Photonic and Power System Assembly.” Since 2011, he has been the Director of the Fraunhofer IZM and responsible for the chair "Nano Interconnect Technologies" at the Technical University Berlin.

Rao R. Tummala, Georgia Institute of Technology, Ph.D., will deliver the keynote on the second day, entitled "Promise and Future of Embedding and Fan-Out Technologies.” All packaging technologies can be classified into two types. Wafer-level packaging (WLP) is one approach with ICs built directly into packages in the wafer fab by simply redistributing the BEOL I/Os and placing bumps. This is the best package electrically, but it is limited to small ICs and to small packages—typically below 5mm. As such, it is limited in external I/Os to connect to the board, typically at 400 microns and above in pitch.

To eliminate the I/O limitation issue, fan-out technology was initially developed in the 1980s and more recently further developed into production by Infineon. But this technology is not a wafer-level packaging, as described above; it is not a continuum of transistors to bumps. It did, however, address the I/O limitation. It is primarily an embedded packaging technology called, eWLP, that allowed fan-out of I/Os, in contrast to WLP, but also enabled embedding to reduce package thickness. This presentation will describe the promise and future of embedding and fan-out technologies.

Prof. Rao Tummala is a Distinguished and Endowed Professor Chair at Georgia Tech. He is well known as an industrial technologist, technology pioneer, and educator. He is the father of LTCC and System-on-Package Technologies.Visit www.iwlpc.com for more information.

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