Electronics Manufacturing Technical Articles

Assembly and Reliability of 1704 I/O FCBGA and FPBGAs

Mar 14, 2013 | Reza Ghaffarian, Ph.D.

Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings....

Publisher: Jet Propulsion Laboratory

Compatibility of Cleaning Agents With Nano-Coated Stencils

Mar 12, 2013 | David Lober and Mike Bixenman, D.B.A.

High density and miniaturized circuit assemblies challenge the solder paste printing process. The use of small components such as 0201, 01005 and μBGA devices require good paste release to prevent solder paste bridging and misalignment. When placing these miniaturized components, taller paste deposits are often required. To improve solder paste deposition, a nano-coating is applied to laser cut stencils to improve transfer efficiency. One concern is the compatibility of the nano-coating with cleaning agents used in understencil wipe and stencil cleaning. The purpose of this research is to test the chemical compatibility of common cleaning agents used in understencil wipe and stencil cleaning processes.Compatibility of Cleaning Agents With Nano-Coated Stencils...

Publisher: KYZEN Corporation

PTH Core-to-Core Interconnect Using Sintered Conductive Pastes

Mar 07, 2013 | Michael Matthews, Ken Holcomb, Jim Haley, Catherine Shearer

The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings...

Publisher: Ormet Circuits, Inc.

Cut Costs and Increase Efficiency with Innovation

Mar 07, 2013 | Pete Doyon, VP of Product Management

No one can deny that organizations across the country have been greatly affected by the decline in the economy. The manufacturing industry is no different. Even now as things seem to be looking up, companies are continually looking to cut costs and increase efficiencies. In addition, these companies must remain compliant with the strict quality and safety standards of the industry, adding even more pressure. Because of this, innovative, automated and easy to use products are needed more than ever before to help companies achieve their goals....

Publisher: Schleuniger, Inc.

Process Issues For Fine Pitch CSP Rework and Scavenging

Mar 04, 2013 | Anthony A. Primavera Ph.D.

Chip-scale (or chip-size) packages are rapidly becoming an important element in electronics due to their size, performance, and cost advantages [Hou, 1998]. The Chip Scale Package (CSP) is becoming a key semiconductor package type, particularly for consumer products. Due to their relatively smaller size, new challenges are presented in the rework and repair of CSPs. (...) The specific focus of this paper is the removal process for rework of CSPs and the site scavenging methods required to properly prepare the circuit board for a new component. Process factors such as the heating, fluxing and, atmosphere are discussed....

Publisher: Universal Instruments Corporation

Effect of Cooling Rate on the Intermetallic Layer in Solder Joints

Feb 28, 2013 | Keith Sweatman, Tetsuro Nishimura, Stuart D. McDonald, Kazuhiro Nogita

While it has long been known that the Cu6Sn5 intermetallic that plays a critical role in the reliability of solder joints made with tin-containing alloys on copper substrates exists in two different crystal forms over the temperature range to which electronics circuitry is exposed during assembly and service, it has only recently been recognized that the change from one form to the other has implications for solder joint reliability. (..) In this paper the authors report a study of the effect of cooling rates on Cu6Sn5 crystals. Cooling rates from 200°C ranged from 10°C/minute to 100°C/minute and the effect of isothermal ageing at intermediate temperatures was also studied. The extent of the phase transformation after each regime was determined using synchrotron X-ray diffraction. The findings have important implications for the manufacture of solder joints and their in-service performance... First published in the 2012 IPC APEX EXPO technical conference proceedings.......

Publisher: Nihon Superior Co., Ltd.

Bringing Rapid Prototyping In-House - A White Paper for RF/Microwave Executives

Feb 22, 2013 | LPKF

Productivity. Innovation. Time to market. Day to day, year over year, businesses are forced to make critical R.O.I.—related decisions that impact the future and the bottom line—some of them reactionary, some forecasted. For a growing number of electronics manufacturers, many of those decisions revolve around whether a function should be performed by an outside contractor or kept in-house. But for many companies in the RF/microwave industry, this decision is often concerned with continuing to employ an outside PCB fabricator for prototype PCBs, or to make a $10,000 to $100,000 investment in an inhouse, rapid PCB prototyping machine that may represent a key competitive advantage....

Publisher: LPKF Laser & Electronics

Boundary Scan Advanced Diagnostic Methods

Feb 14, 2013 | Christopher Cain

Boundary-scan (1149.1) technology was originally developed to provide a far easier method to perform digital DC testing to detect intra-IC interconnect assembly faults, such as solder shorts and opens. Today's advanced IC technology now includes high-speed differential interfaces that include AC or DC coupling components loaded on the printed circuit assembly. Simple stuck-at-high/low test methods are not sufficient to detect all assembly fault conditions, which includes shorts, opens and missing components. Improved diagnostics requires detailed circuit analysis, predictive assembly fault simulation and more complex testing to isolate and accurately detect all possible assembly faults... First published in the 2012 IPC APEX EXPO technical conference proceedings...

Publisher: Agilent Technologies, Inc.

Avoiding the Solder Void

Feb 08, 2013 | Richard Lathrop

Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed....

Publisher: Heraeus

Effect of Silicone Contamination on Assembly Processes

Feb 07, 2013 | John Meyer and Carlyn A. Smith, Ph.D.

Silicone contamination is known to have a negative impact on assembly processes such as soldering, adhesive bonding, coating, and wire bonding. In particular, silicone is known to cause de-wetting of materials from surfaces and can result in adhesive failures. There are many sources for silicone contamination with common sources being mold releases or lubricants on manufacturing tools, offgassing during cure of silicone paste adhesives, and residue from pressure sensitive tape. This effort addresses silicone contamination by quantifying adhesive effects under known silicone contaminations. The first step in this effort identified an FT-IR spectroscopic detection limit for surface silicone utilizing the area under the 1263 cm-1 (Si-CH3) absorbance peak as a function of concentration (µg/cm2). The next step was to pre-contaminate surfaces with known concentrations of silicone oil and assess the effects on surface wetting and adhesion. This information will be used to establish guidelines for silicone contamination in different manufacturing areas within Harris Corporation... First published in the 2012 IPC APEX EXPO technical conference proceedings....

Publisher: Harris Corporation

Projection Moiré vs. Shadow Moiré for Warpage Measurement and Failure Analysis of Advanced Packages

Jan 31, 2013 | Joe Thomas

There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices, the emergence of lead-free processing, and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide. First published in the 2012 IPC APEX EXPO technical conference proceedings...

Publisher: ZN Technologies

Inline Wire and Cable Identification

Jan 30, 2013 | Pete Doyon, VP of Product Management

Many OEM’s require that individual wires and cables used in their products be clearly identified with a mark or label. For some, such as in the military and aerospace markets, wire and cable identification (or “wire ID”) is mandatory and the process is governed by stringent specifications, such as SAE AS50881 (formerly MIL5088L). For others, the decision to use wire ID is a voluntary one. This article will describe what type of information is typically identified on wire and cables, concepts for improved productivity, what types of systems are available and the pros and cons of each....

Publisher: Schleuniger, Inc.

Choosing the Right Cutting and Stripping Machine – It’s all about the apps

Jan 29, 2013 | Pete Doyon, VP Product Management

Choosing a new wire Cutting and Stripping (C&S) machine can be like shopping for a new car. With so many choices, where does one start? A nice, little sports car might be fun to have, but how often will it just sit there because it can’t carry a car load of kids or some odd-sized goods from the local home improvement store? You just might be better off with a midsize SUV that does a pretty good job at doing everything you need it to do....

Publisher: Schleuniger, Inc.

Internet Marketing Article 01-24-2013

Jan 24, 2013 | Roland Girouard

Being found in the search engines for a wide variety of terms directly related to my business would be my 1st priority......

Publisher: SMTnet

An investigation into low temperature tin-bismuth and tin-bismuth-silver lead-free alloy solder pastes for electronics manufacturing applications

Jan 24, 2013 | Jasbir Bath, Manabu Itoh, Gordon Clark, Hajime Takahashi, Kyosuke Yokota, Kentaro Asai, Atsushi Irisawa, Kimiaki Mori, David Rund, Roberto Garcia

The electronics industry has mainly adopted the higher melting point Sn3Ag0.5Cu solder alloys for lead-free reflow soldering applications. For applications where temperature sensitive components and boards are used this has created a need to develop low melting point lead-free alloy solder pastes. Tin-bismuth and tin-bismuth-silver containing alloys were used to address the temperature issue with development done on Sn58Bi, Sn57.6Bi0.4Ag, Sn57Bi1Ag lead-free solder alloy pastes. Investigations included paste printing studies, reflow and wetting analysis on different substrates and board surface finishes and head-in-pillow paste performance in addition to paste-in-hole reflow tests. Voiding was also investigated on tin-bismuth and tin-bismuth-silver versus Sn3Ag0.5Cu soldered QFN/MLF/BTC components. Mechanical bond strength testing was also done comparing Sn58Bi, Sn37Pb and Sn3Ag0.5Cu soldered components. The results of the work are reported....

Publisher: Christopher Associates Inc.

Brief description of ENIG for Multilayer PCB

Jan 18, 2013 | Grace

ENIG (Electroless Nickel/Immersion Gold) is to deposit nickel gold plating which has good solderability, wear resistance , leveling appearance and small electric resistance. It included 4 steps that are pretreatment, immersion nickel, immersion gold and Post treatment......

Publisher: Everest PCB equipment Co.,Ltd

Solving the ENIG Black Pad Problem: An ITRI Report on Round 2

Jan 17, 2013 | F.D.Bruce Houghton

A problem exists with electroless nickel / immersion gold (ENIG) surface finish on some pads, on some boards, that causes the solder joint to separate from the nickel surface, causing an open. The solder has wet and dissolved the gold. A weak tin to nickel intermetallic bond initially occurs, but the intermetallic bond cracks and separates when put under stress. Since the electroless nickel / immersion gold finish performs satisfactory in most applications, there had to be some area within the current chemistry process window that was satisfactory. The problem has been described as a 'BGA Black Pad Problem' or by HP as an 'Interfacial Fracture of BGA Packages…'[1]. A 24 variable experiment using three different chemistries was conducted during the ITRI (Interconnect Technology Research Institute) ENIG Project, Round 1, to investigate what process parameters of the chemical matrix were potentially satisfactory to use and which process parameters of the chemical matrix need to be avoided. The ITRI ENIG Project has completed Round 1 of testing and is now in the process of Round 2 TV (Test Vehicle) build....

Publisher: Celestica Corporation

Identification and Prevention of "Black Pad"

Jan 17, 2013 | Kong Hui Lee

The use of an electroless nickel, immersion gold (ENIG) surface finish comes with the inherent potential risk of Black Pad failures that can cause fracture embrittlement at the interface between the solder and the metal pad. As yet, there is no conclusive agreed solution to effectively eliminate Black Pad failures. The case studies presented are intended to add to the understanding of the Black Pad failure mechanism and to identify both the plating and the subsequent assembly processes and conditions that can help to prevent the likelihood of Black Pad occurring....

Publisher: Jabil Circuit, Inc.

Electroformed vs. Laser-cut: A Stencil Performance Study

Jan 11, 2013 | By Michael R. Burgess and William E. Coleman, Ph.D., Photo Stencil

There have been claims in the industry that laser-cut electroformed nickel foil blanks provide stencil print performance comparable to electroformed stencils. A study was established to measure the quantitative differences in performance between the two during an independent lab study....

Publisher: Photo Stencil LLC

The Application of Spherical Bend Testing to Predict Safe Working Manufacturing Process Strains

Jan 09, 2013 | John McMahon P.Eng, Brian Gray P.Eng,

The increased temperatures associated with lead free processes have produced significant challenges for PWB laminates. Newly developed laminates have different curing processes, are commonly filled with ceramic particles or micro-clays and can have higher Tg values. These changes designed to reduce Z-axis expansion and improve the materials resistance to thermal excursions through primary attach and rework operations have also produced harder resin systems with reduced fracture toughness....

Publisher: Celestica Corporation

The Conditions and Solutions of Lead-free Hand Soldering

Jan 05, 2013 | Huang Xin

More and more countries legislate to forbib lead usage in solder material. However, the lead-free solder wire has higher melting point and soldering temperature, increase soldering iron temperature may damage the PCB or components. How to solve this problem?...

Publisher: Leisto Industrial Co., Limited

Investigation of Pad Cratering in Large Flip-Chip BGA using Acoustic Emission

Jan 03, 2013 | Anurag Bansal, Cherif Guirguis, Kuo-Chuan Liu

Electronics assemblies with large flip-chip BGA packages can be prone to either pad cratering or brittle intermetallic (IMC) failures under excessive PCB bending. Pad cratering cracks are not detected by electrical testing or non-destructive inspection methods, yet they pose a long term reliability risk since the cracks may propagate under subsequent loads to cause electrical failure. Since the initiation of pad cratering does not result in an instantaneous electrical signature, detecting the onset of this failure has been challenging. An acoustic emission methodology was recently developed by the authors to detect the onset of pad cratering. The instantaneous release of elastic energy associated with the initiation of an internal crack, i.e., Acoustic Emission (AE), can be monitored to accurately determine the onset of both pad cratering and brittle intermetallic (IMC) failures....

Publisher: Cisco Systems, Inc.

Advances in Conductive Inks across Multiple Applications and Deposition Platforms

Dec 27, 2012 | Scott E. Gordon, Jay R. Dorfman, Daniel Kirk, Kerry Adams

Printed Electronics is generally defined as the patterning of electronic materials, in solution form, onto flexible substrates, omitting any use of the photolithography, etching, and plating steps commonly found within the Printed Circuit Board (PCB) industry. The origins of printed electronics go back to the 1960s, and close variants of several original applications and market segments remain active today. Through the 1980s and 1990s Printed Electronic applications based on Membrane Touch Switch and Electroluminescent lighting technologies became common, and the screen printed electronic materials used then have formed the building blocks for many of the current and emerging technologies and applications... First published in the 2012 IPC APEX EXPO technical conference proceedings....

Publisher: DuPont

Types of flexible printed circuit board

Dec 26, 2012 | Grace Yang

①Single side The basic flexible printed circuit board is used of substrate of single side pcb materials and coated coverlay after finishing printed. ②Double sided That is made of substrates of double sided printed circuit board with double surface coated coverlays after finishing printed. ③Single copper foil with double coverlays Single copper foil coated different coverlays with double surface after finishing printed. ④Air gap Laminating two single printed circuit board together with no glue and bare design to meet high flexibility requirements. ⑤Multilayer That is designed for three and above circuit layers by laminating single side printed circuit board or double sided printed circuit board. ⑥COF IC chips and electronic components are installed on the flexible circuit board directly. ⑦Rigid-Flexible PCB Combined to rigid PCB with supporting and flexible PCB with high flexibility. ...

Publisher: Everest PCB equipment Co.,Ltd

Principles of Analog In-Circuit Testing

Dec 26, 2012 | Anthony J. Suto, Teradyne

Passive components including resistors, capacitors, inductors, and circuit-protection devices compose the highest percentage of all devices that are populated on today’s PCB assemblies. However, the successful isolation and testing of these components during ICT is perhaps the most challenging and the least understood of all modern-day validation practices....

Publisher: Teradyne

Advantages of Bismuth-based Alloys for Low Temperature Pb-Free Soldering and Rework

Dec 20, 2012 | Brook Sandy, Edward Briggs and Ronald Lasky, Ph.D.

The increased function of personal electronic devices, such as mobile phones and personal music devices, has driven the need for smaller and smaller active and passive components. This trend toward miniaturization, occurring at the same time as the conversion to RoHS-compliant lead-free assembly, has been a considerable challenge to the electronics assembly industry. The main reason for this is the higher reflow process temperatures required for Pb-free assembly. These higher temperatures can thermally damage the PCB and the components. In addition, the higher reflow temperatures can negatively affect the solder joint quality, especially when coupled with the smaller paste deposits required for these smaller components. If additional thermal processing is required, the risk increases even more. First Published at SMTA's International Conference on Soldering and Reliability in Toronto, May 2011...

Publisher: Indium Corporation

Throughput vs. Wet-Out Area Study for Package on Package (PoP) Underfill Dispensing

Dec 17, 2012 | Brad Perkins, Jared Wilburn

Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process....

Publisher: ASYMTEK Products | Nordson Electronics Solutions

Investigation of Device Damage Due to Electrical Testing

Dec 14, 2012 | Rosa Croughwell and John McNeill, Worcester Polytechnic Institute

This paper examines the potential failure mechanisms that can damage modern lowvoltage CMOS devices and their relationship to electrical testing. Failure mechanisms such as electrostatic discharge (ESD), CMOS latch-up, and transistor gate oxide degradation can occur as a result of electrical over-voltage stress (EOS). In this paper, EOS due to electrical testing is examined and an experiment is conducted using pulsed voltage waveforms corresponding to conditions encountered during in-circuit electrical testing. Experimental results indicate a correlation between amplitude and duration of the pulse waveform and device degradation due to one or more of the failure mechanisms....

Publisher: Worcester Polytechnic Institute

Issues and Challenges of Testing Modern Low Voltage Devices with Conventional In-Circuit Testers

Dec 14, 2012 | Alan J. Albee

The popularity of low voltage technologies has grown significantly over the last decade as semiconductor device manufacturers have moved to satisfy market demands for more powerful products, smaller packaging, and longer battery life. By shrinking the size of the features they etch into semiconductor dice, IC manufacturers achieve lower costs, while improving speed and building in more functionality. However, this move toward smaller features has lead to lower breakdown voltages and increased opportunities for component overstress and false failures during in-circuit test....

Publisher: Teradyne

Designing PCBs for Test and Inspection

Dec 14, 2012 | Michael J. Smith, Teradyne

This article provides practical and affordable Design-for- Test (DFT) and Design-for-Inspection (DFI) methods that will have a positive impact on product costs, yield, reliability, and time-to-market. The properties of testability (including controllability and observability) will be analysed as they relate to analogue and digital design rules and their cause/effect, as well as the electrical and physical characteristics of proper PCB design....

Publisher: Teradyne

Characterization of No Clean Solderpaste Residues: The Relationship to In-Circuit Testing

Dec 14, 2012 | Merlin Kister

This paper will describe the various residues that are now available in the market with their compatibility to in-circuit testing. This paper will also cover a new paste development that has been made to completely address the issue of probe testing for all manufacturers no matter what their testing requirements are....

Publisher:

Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish

Dec 13, 2012 | Dong-Won Shin, Jin-Woo Heo, Yeonseop Yu, Jong-Soo Yoo, Pyoung-Woo Cheon, Seon-Hee Lee

First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4....

Publisher: Samsung Electro-Mechanics

How to improve reliability of PCB equipments

Dec 12, 2012 | Grace Yang

When we designed the PCB equipments, we should try to simplify crcuit and structure design that on the premise of ensuring the equipments to meet the technology and performance, In modern society, modules design (MD)is a effective measures to improved the pcb equipment reliability. The system were made up simpleness functions of modules to reducing the complexity of the design. Both domestic and abroad, a large number of facts have proved this point, MD was a best choice for PCB equipment design....

Publisher: Everest PCB equipment Co.,Ltd

Void Detection in Large Solder Joints of Integrated Power Electronics

Dec 06, 2012 | Patrick Schuchardt

Inspection of integrated power electronics equals sophisticated test task. X-ray inspection based on 2D / 2.5D principles not utilizable. Full 3D inspection with adapted image capturing and reconstruction is necessary for test task.... First published in the 2012 IPC APEX EXPO technical conference proceedings. ...

Publisher: GOEPEL Electronic

Overcoming Logistic, Economic and Technical Challenges to Implementing Functional Test in High Mix / High Volume Production Environments

Nov 29, 2012 | Craig T. Pynn

First published in the 2012 IPC APEX EXPO technical conference proceedings... Functional circuit test (FCT) of circuit boards and end products in a high volume (>1000 units per day) production environment presents challenging technical, logistic and cost obstacles that are usually more complex than those encountered at the inspection (automated optical inspection) and the manufacturing process test step (in-circuit test)....

Publisher: SiFO Technologies

Effective Qualification of Soldering Iron Performance Criteria

Nov 27, 2012 | Metcal

Quality managers and line supervisors are routinely tasked with the responsibility of ensuring that the hand soldering process is under control. The method most commonly used is to measure the idle tip temperature of the soldering station and to use this reading as a benchmark of system compliance. This method, although popular is now being seriously questioned by many industry professionals as being irrelevant in qualifying true system process control.

This document aims to present a practical view of what factors are important for successful hand soldering and to suggest an alternative procedure for qualification that is simple, repeatable and directly related to the effectiveness of the soldering station....

Publisher: Metcal

Precision Cleaning in 21st Century: New Solvent with Low Global Warming Potential

Nov 15, 2012 | Rajat Basu, Ryan Hulse, Kane Cook, Diana Mercier

First published in the 2012 IPC APEX EXPO technical conference proceedings. As we progress in the 21st century, electronics manufacturing will need more and more precision. Parts will get more complex since more components have to be assembled in smaller spaces. Circuit boards and other electronic assemblies will become more densely populated; spacings between components will be shorter. This will require precision manufacturing and efficient cleaning during and post manufacturing. In addition, with population and technology progressing, larger amount of greenhouse gases will be emitted resulting in higher global warming. Intense research effort is going on to develop new generation of chemicals to address both cleaning and global warming issues. Low global warming solutions in refrigeration and as insulating agents are already in the marketplace....

Publisher: Honeywell International

Increase Your Process Control and Lower Cost of Ownership

Nov 12, 2012 | Ed Zamborsky, Eastern Territory Sales Manager, OK International/Metcal

With consumers constantly looking for lower prices on their technology products and manufacturers trying to squeak out higher margins from their production lines, the need for process control and lower overhead costs have become even more important. One sector that is often overlooked is the hand soldering area of the factory. Many factories have been struggling with antiquated soldering systems for years. In some cases they are trying to make their investment in stations last much longer than they were designed for, or they are falsely trying to recoup their original investment ‐ all at the cost of higher operating expenses or even worse, reduced operator thru‐put....

Publisher: Metcal

Elemental Compositions of Over Two Dozen Cell Phones

Nov 08, 2012 | Bev Christian, Irina Romanova, Laura Turbini

first published in the 2012 IPC APEX EXPO technical conference proceedings. Twenty-nine different cells phones have been disassembled, ground up, dissolved and analyzed for elemental content, mainly for information about the metals present in the phones, but also for some metalloids and non-metals. The paper will discuss the method used and propose possible sources in the telephones for certain elements of interest and the reasons for the interest in some of the elements....

Publisher: Research In Motion

Polyphenylene Ether Macromonomers. XI. Use in Non-Epoxy Printed Wiring Boards

Nov 01, 2012 | Edward N. Peters, Scott M. Fisher, Hua Guo

First published in the 2012 IPC APEX EXPO technical conference proceedings. The continuous progression toward portable, high frequency microelectronic systems has placed high demands on material performance, notably low dielectric constants (Dk), low loss tangent (Df), low moisture uptake, and good thermal stability. Epoxy resins are the workhorses of the electronic industry. Significant performance enhancements have been obtained through the use of PPE telechelic macromonomers with epoxy resins. However, there is a ceiling on the performance obtainable from epoxy-based resins. Therefore, non-epoxy based dielectric materials are used to fulfill the need for higher performance....

Publisher: SABIC

Stencil Printing of Small Apertures

Oct 25, 2012 | William E. Coleman Ph.D.

First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper will examine stencil technologies (including Laser and Electroform), Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings), and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated....

Publisher: Photo Stencil LLC

Lead-free SMT Soldering Defects How to Prevent Them

Oct 23, 2012 | Peter Biocca, Senior Development Engineer

Tin-Silver-Copper alloys are the primary choice for lead-free SMT assembly. Although there are other options available such as alloys containing bismuth or indium and other elements, tin-silver-copper solders, also known as SAC alloys are by far the most popular. They are used by approximately 65% of users, as last surveyed by Soldertec in 2003....

Publisher: Kester

The Morphology Evolution and Voiding of Solder Joints on QFN Central Pads with a Ni/Au Finish

Oct 18, 2012 | Julie Silk, Jianbiao Pan, Mike Powers

First published in the 2012 IPC APEX EXPO technical conference proceedings. In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish....

Publisher: Agilent Technologies, Inc.

Wire Bonding and Soldering on Enepig and Enep Surface Finishes with Pure Pd-Layers

Oct 11, 2012 | Mustafa Özkök, Joe McGurran, Dieter Metzger, Hugh Roberts

First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper shows the benefits by using a pure palladium Layer in the ENEPIG (Electroless Nickel, Electroless Palladium, Immersion Gold) and ENEP (Electroless Nickel, Electroless P...

Publisher: Atotech

Reliability of BGA Solder Joints after Re-Balling Process

Oct 04, 2012 | M.H. Biglaria, A. Nazariana, R. Denteneera, M. Biglari, Jra, A.A. Kodentsov

First published in the 2012 IPC APEX EXPO technical conference proceedings... Due to the obsolescence of SnPb BGA components, electronics manufacturers that use SnPb solder paste either have to use lead-free BGAs and adjust the reflow process or re-ball t...

Publisher: Mat-tech

A Novel Material for High Layer Count and High Reliability Printed Circuit Boards

Sep 27, 2012 | Jie Wan, Junqi Tang, Xianping Zeng

First published in the 2012 IPC APEX EXPO technical conference proceedings. Over the past few years a new family of laminate systems has been developed to face the increasing physical demands of withstanding Pb-free soldering processes used in the assembl...

Publisher: Shengyi Technology Co., Ltd.

Evaluation of Laminates in Pb-free HASL Process and Pb-free Assembly Environment

Sep 20, 2012 | Khaw Mei Ming, Andrey Lee

First published in the 2012 IPC APEX EXPO technical conference proceedings. An evaluation of four FR4 laminates in commonly used stack-ups was done to determine their survivability for the Pb-free HASL process followed by a worst case Pb-free manufacturin...

Publisher: Agilent Technologies, Inc.

Thermal Cycle Reliability Study of Vapor Phase BGA Solder Joints

Sep 13, 2012 | Ward Gatza; Agilent Technologies, Inc., Tom Evans; Thomas C. Evans Consulting

First published in the 2012 IPC APEX EXPO technical conference proceedings. Prior to committing production boards to vapor phase soldering, we performed an evaluation to assess reliability and evaluate the vacuum soldering option. The reliability of vapor...

Publisher: Agilent Technologies, Inc.

Pad Cratering - The Invisible Threat to the Electronics Industry

Sep 06, 2012 | Chris Hunrath

First published in the 2012 IPC APEX EXPO technical conference proceedings. Pad Cratering opens circuits. This occurs when the resin crack (fracture) migrates through a copper trace or via. This happens at assembly, in service or during handling. When com...

Publisher: Integral Technology, Inc

Inclusion Voiding in Gull Wing Solder Joints

Aug 30, 2012 | T.L. Lewis, C.O. Ndiaye, J.R. Wilcox

This paper provides definitions of the different voiding types encountered in Gull Wing solder joint geometries. It further provides corresponding reliability data that support some level of inclusion voiding in these solder joints and identifies the final criteria being applied for certain IBM Server applications. Such acceptance criteria can be applied using various available x-ray inspection techniques on a production or sample basis. The bulk of supporting data to date has been gathered through RoHS server exempt SnPb eutectic soldering operations but it is expected to provide a reasonable baseline for pending Pb-free solder applications....

Publisher: IBM Corporation