May 30, 2016 | Zhen Feng, Ph. D., David Geiger, Weifeng Liu, Ph. D., Anwar Mohammed, Murad Kurwa, AEG, Flextronics, George Tint Ph. D., Saki America.
As a part of series of studies on X-Ray inspection technology to quantify solder defects in BGA balls, we have conducted inspection of 3 level POP package by using a new AXI that capable of 3D-CT imaging. The new results are compared with the results of earlier AXI measurements. It is found that 3D measurements offer better defect inspection quality, lower false call and escapes....
Publisher: Flex (Flextronics International)
May 26, 2016 | J. Servin, P. Gomez, M. Dominguez, A. Aragon
The oxide layers are known as wetting inhibitors in component and PCB metallizations. The oxide acts as barrier that prevent the tin diffusion from happening. Besides, in corrosion studies, the role of salt residues -with Cl ion- on some metals is known as being promoters of oxidation or corrosion. On the other hand, most of corrosion studies with tin metallization are focused mainly on the corrosion resistance of tin alloys, but little has been done respecting to the influence of salts on tin metallization wetting.
In this paper, a series of experiments was carried over to know the influence of specifically NaCl on BGA wetting given Head in Pillow (HiP) as result....
Publisher: Continental Corporation
May 19, 2016 | Erik Olson, Molly Smith, Greg Marszalek, Karl Manske
As consumers become more reliant on their handheld electronic devices and take them into new environments, devices are increasingly exposed to situations that can cause failure. In response, the electronics industry is making these devices more resistant to environmental exposures. Printed circuit board assemblies, handheld devices and wearables can benefit from a protective conformal coating to minimize device failures by providing a barrier to environmental exposure and contamination.
Traditional conformal coatings can be applied very thick and often require thermal or UV curing steps that add extra cost and processing time compared to alternative technologies. These coatings, due to their thickness, commonly require time and effort to mask connectors in order to permit electrical conductivity. Ultra-thin fluorochemical coatings, however, can provide excellent protection, are thin enough to not necessarily require component masking and do not necessarily require curing.
In this work, ultra-thin fluoropolymer coatings were tested by internal and industry approved test methods, such as IEC (ingress protection), IPC (conformal coating qualification), and ASTM (flowers-of-sulfur exposure), to determine whether this level of protection and process ease was possible....
Publisher: 3M Company
May 13, 2016 | Lior Yosef
The process of manufacturing and qualifying IC's consists of many steps while Temperature forcing systems play a crucial role in the final testing process. These environmental tests assure quality and reliability by stressing the device on one hand as well as helping to characterize and validate it on the other hand (making sure manufacturing outcome meets the design requirements). At later stages the temperature testing can support failure analysis effort and root cause analysis. AS common practice we are dealing with few different kinds of temperature forcing systems: Chambers, Thermal Stream systems and Direct Thermal Head systems. In this article I would like to focus on the practical aspects of utilizing Thermal Stream systems and Direct Thermal Head systems....
Publisher: Mechanical Devices
May 12, 2016 | Yan Ning, Michael H. Azarian, Michael Pecht
Advances in miniaturized electronic devices have led to the evolution of microvias in high density interconnect (HDI) circuit boards from single-level to stacked structures that intersect multiple HDI layers. Stacked microvias are usually filled with electroplated copper. Challenges for fabricating reliable microvias include creating strong interface between the base of the microvia and the target pad, and generating no voids in the electrodeposited copper structures. Interface delamination is the most common microvia failure due to inferior quality of electroless copper, while microvia fatigue life can be reduced by over 90% as a result of large voids, according to the authors’ finite element analysis and fatigue life prediction. This paper addresses the influence of voids on reliability of microvias, as well as the interface delamination issue. ...
The largest electronic products research center focused on electronics reliability, is dedicated to providing a knowledge and resource base to support the development of competitive electronic components, products and systems.
College Park, Maryland, USA
May 05, 2016 | Michael Ford.
For many years, manufacturing has sought to increase competitiveness by moving off-shore to countries with lower labour costs. Electronic manufacturing services (EMS) companies provided an essential element to make off-shore transfer happen more quickly, offering further cost reduction opportunities from load balancing. Fierce arguments were put forward to protect the loss of local jobs, although the result was, in almost all cases, inevitable. Today, however, the whole market of PCBbased electronics products has changed significantly. The "pros" of off-shoring are no longer what they once were, and the "cons" are becoming more significant because off-shore manufacturing can no longer satisfy the needs of the market.
In this paper, we expose the real costs of off-shore manufacturing, and put labour cost differentials into perspective. We demonstrate how practically, using existing technologies, re-shored manufacturing can yield better business return, either for an OEM, or through EMS providers....
Publisher: Mentor Graphics
Apr 28, 2016 | Julien Perraud, Arnaud Grivon.
Underfilling is a long-standing process issued from the micro-electronics that can enhance the robustness and the reliability of first or second-level interconnects for a variety of electronic applications. Its usage is currently spreading across the industry fueled by the decreasing reliability margins induced by the miniaturization and interconnect pitch reduction. (...)
This paper will address the control of surface mount under filled assemblies, focusing on applicable inspection techniques and possible options to overcome their limitations....
Apr 21, 2016 | David Geiger, Georgie Thein; AEG, Flextronics International Inc.
The world of electronics continues to increase functional densities on products. One of the ways to increase density of a product is to utilize more of the 3 dimensional spaces available. Traditional printed circuit boards utilize the x/y plane and many miniaturization techniques apply to the x/y space savings, such as smaller components, finer pitches, and closer component to component distances.
This paper will explore the evolution of 3D assembly techniques, starting from flexible circuit technology, cavity assembly, embedded technology, 3 dimensional surface mount assembly, etc....
Publisher: Flex (Flextronics International)
Apr 14, 2016 | Louis Y. Ungar
A system level test, usually built-in test (BIT), determines that one or more subsystems are faulty. These subsystems sent to the depot or factory repair facility, called units under test (UUTs) often pass that test, an event we call No-Fault-Found (NFF). With more-and more electronics monitored by BIT, it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA), cannot duplicate (CNDs)or retest OK (RTOK) events. NFFs at the depot are caused by FAs, CNDs, RTOKs as well as a number of other complications. Attempting to repair NFF scan waste precious resources, compromise confidence in the product, create customer dissatisfaction, and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action at the system level are invalid. NFFs can be caused by real failures or may be a result of system level false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs.
This paper will shed some light on this trade-off. Finally, we will explore approaches for dealing with the NFF issue in a cost effective manner....
Publisher: A.T.E. Solutions, Inc.
The leading Test, ATE and Testability consulting and educational firm, offering various test related courses. Maintains the BestTest Directory, a test community knowledge base. Publishes The BestTest eNewsletter.
Los Angeles, California, USA
Apr 08, 2016 | Julian Coates
PCB assembly designs become more complex year-on-year, yet early-stage form/fit compliance verification of all designed-in components to the intended manufacturing processes remains a challenge. So long as librarians at the design and manufacturing levels continue to maintain their own local standards for component representation, there is no common representation in the design-to-manufacturing phase of the product lifecycle that can provide the basis for transfer of manufacturing process rules to the design level. A comprehensive methodology must be implemented for all component types, not just the minority which happen to conform to formal packaging standards, to successfully left-shift assembly and test DFM analysis to the design level and thus compress NPI cycle times.(...)
This paper will demonstrate the technological components of the working solution: the logic for deriving repeatable and standardized package and pin classifications from a common source of component physical-model content, the method for associating DFA and DFT rules to those classifications, and the transfer of those rules to separate DFM and NPI analysis tools elsewhere in the design-through-manufacturing chain resulting in a consistent DFM process across multiple design and manufacturing organizations....
Publisher: Mentor Graphics