Mar 21, 2013 | C.P. Hunt, O. Thomas, D. Di Maio, E. Kamara, H. Lu
This paper explores the behaviour of a copper test vehicle with multiple reflowed solder joints, which has direct relevance to ball grid arrays (BGA) and high density interconnect structures. The paper explores the relative stress conditions on the distributed joints and the sensitivity to ball joint shape... First published in the 2012 IPC APEX EXPO technical conference proceedings...
Publisher: National Physical Laboratory
Mar 14, 2013 | Reza Ghaffarian, Ph.D.
Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings....
Publisher: Jet Propulsion Laboratory
Mar 12, 2013 | David Lober and Mike Bixenman, D.B.A.
High density and miniaturized circuit assemblies challenge the solder paste printing process. The use of small components such as 0201, 01005 and μBGA devices require good paste release to prevent solder paste bridging and misalignment. When placing these miniaturized components, taller paste deposits are often required. To improve solder paste deposition, a nano-coating is applied to laser cut stencils to improve transfer efficiency. One concern is the compatibility of the nano-coating with cleaning agents used in understencil wipe and stencil cleaning. The purpose of this research is to test the chemical compatibility of common cleaning agents used in understencil wipe and stencil cleaning processes.Compatibility of Cleaning Agents With Nano-Coated Stencils...
Publisher: KYZEN Corporation
Mar 07, 2013 | Michael Matthews, Ken Holcomb, Jim Haley, Catherine Shearer
The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings...
Publisher: Ormet Circuits, Inc.
Manufacturer of sintering, electrically conductive materials. Applications include semiconductor die attach, component attach, via fill, z-axis interconnection, conductive lines and traces and plated-through hole fill.
San Diego, California, USA
Mar 07, 2013 | Pete Doyon, VP of Product Management
No one can deny that organizations across the country have been greatly affected by the decline in the economy. The manufacturing industry is no different. Even now as things seem to be looking up, companies are continually looking to cut costs and increase efficiencies. In addition, these companies must remain compliant with the strict quality and safety standards of the industry, adding even more pressure. Because of this, innovative, automated and easy to use products are needed more than ever before to help companies achieve their goals....
Publisher: Schleuniger, Inc.
Mar 04, 2013 | Anthony A. Primavera Ph.D.
Chip-scale (or chip-size) packages are rapidly becoming an important element in electronics due to their size, performance, and cost advantages [Hou, 1998]. The Chip Scale Package (CSP) is becoming a key semiconductor package type, particularly for consumer products. Due to their relatively smaller size, new challenges are presented in the rework and repair of CSPs. (...) The specific focus of this paper is the removal process for rework of CSPs and the site scavenging methods required to properly prepare the circuit board for a new component. Process factors such as the heating, fluxing and, atmosphere are discussed....
Publisher: Universal Instruments Corporation
Feb 28, 2013 | Keith Sweatman, Tetsuro Nishimura, Stuart D. McDonald, Kazuhiro Nogita
While it has long been known that the Cu6Sn5 intermetallic that plays a critical role in the reliability of solder joints made with tin-containing alloys on copper substrates exists in two different crystal forms over the temperature range to which electronics circuitry is exposed during assembly and service, it has only recently been recognized that the change from one form to the other has implications for solder joint reliability. (..) In this paper the authors report a study of the effect of cooling rates on Cu6Sn5 crystals. Cooling rates from 200°C ranged from 10°C/minute to 100°C/minute and the effect of isothermal ageing at intermediate temperatures was also studied. The extent of the phase transformation after each regime was determined using synchrotron X-ray diffraction. The findings have important implications for the manufacture of solder joints and their in-service performance... First published in the 2012 IPC APEX EXPO technical conference proceedings.......
Publisher: Nihon Superior Co., Ltd.
Nihon has been a leader in soldering and brazing since 1966. Nihon manufactures SMT solder joining materials e.g. lead-free solder (SN100C:Sn-Cu-Ni-Ge etc): solder paste, solder spheres, flux cored solder wire, solder bar, etc.
Feb 22, 2013 | LPKF
Productivity. Innovation. Time to market. Day to day, year over year, businesses are forced to make critical R.O.I.—related decisions that impact the future and the bottom line—some of them reactionary, some forecasted. For a growing number of electronics manufacturers, many of those decisions revolve around whether a function should be performed by an outside contractor or kept in-house. But for many companies in the RF/microwave industry, this decision is often concerned with continuing to employ an outside PCB fabricator for prototype PCBs, or to make a $10,000 to $100,000 investment in an inhouse, rapid PCB prototyping machine that may represent a key competitive advantage....
Publisher: LPKF Laser & Electronics
Feb 14, 2013 | Christopher Cain
Boundary-scan (1149.1) technology was originally developed to provide a far easier method to perform digital DC testing to detect intra-IC interconnect assembly faults, such as solder shorts and opens. Today's advanced IC technology now includes high-speed differential interfaces that include AC or DC coupling components loaded on the printed circuit assembly. Simple stuck-at-high/low test methods are not sufficient to detect all assembly fault conditions, which includes shorts, opens and missing components. Improved diagnostics requires detailed circuit analysis, predictive assembly fault simulation and more complex testing to isolate and accurately detect all possible assembly faults... First published in the 2012 IPC APEX EXPO technical conference proceedings...
Publisher: Agilent Technologies, Inc.
Feb 08, 2013 | Richard Lathrop
Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed....