Electronics Manufacturing Technical Articles

Throughput vs. Wet-Out Area Study for Package on Package (PoP) Underfill Dispensing

Dec 17, 2012 | Brad Perkins, Jared Wilburn

Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process....

Publisher: ASYMTEK Products | Nordson Electronics Solutions

Investigation of Device Damage Due to Electrical Testing

Dec 14, 2012 | Rosa Croughwell and John McNeill, Worcester Polytechnic Institute

This paper examines the potential failure mechanisms that can damage modern lowvoltage CMOS devices and their relationship to electrical testing. Failure mechanisms such as electrostatic discharge (ESD), CMOS latch-up, and transistor gate oxide degradation can occur as a result of electrical over-voltage stress (EOS). In this paper, EOS due to electrical testing is examined and an experiment is conducted using pulsed voltage waveforms corresponding to conditions encountered during in-circuit electrical testing. Experimental results indicate a correlation between amplitude and duration of the pulse waveform and device degradation due to one or more of the failure mechanisms....

Publisher: Worcester Polytechnic Institute

Issues and Challenges of Testing Modern Low Voltage Devices with Conventional In-Circuit Testers

Dec 14, 2012 | Alan J. Albee

The popularity of low voltage technologies has grown significantly over the last decade as semiconductor device manufacturers have moved to satisfy market demands for more powerful products, smaller packaging, and longer battery life. By shrinking the size of the features they etch into semiconductor dice, IC manufacturers achieve lower costs, while improving speed and building in more functionality. However, this move toward smaller features has lead to lower breakdown voltages and increased opportunities for component overstress and false failures during in-circuit test....

Publisher: Teradyne

Designing PCBs for Test and Inspection

Dec 14, 2012 | Michael J. Smith, Teradyne

This article provides practical and affordable Design-for- Test (DFT) and Design-for-Inspection (DFI) methods that will have a positive impact on product costs, yield, reliability, and time-to-market. The properties of testability (including controllability and observability) will be analysed as they relate to analogue and digital design rules and their cause/effect, as well as the electrical and physical characteristics of proper PCB design....

Publisher: Teradyne

Characterization of No Clean Solderpaste Residues: The Relationship to In-Circuit Testing

Dec 14, 2012 | Merlin Kister

This paper will describe the various residues that are now available in the market with their compatibility to in-circuit testing. This paper will also cover a new paste development that has been made to completely address the issue of probe testing for all manufacturers no matter what their testing requirements are....

Publisher:

Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish

Dec 13, 2012 | Dong-Won Shin, Jin-Woo Heo, Yeonseop Yu, Jong-Soo Yoo, Pyoung-Woo Cheon, Seon-Hee Lee

First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4....

Publisher: Samsung Electro-Mechanics

How to improve reliability of PCB equipments

Dec 12, 2012 | Grace Yang

When we designed the PCB equipments, we should try to simplify crcuit and structure design that on the premise of ensuring the equipments to meet the technology and performance, In modern society, modules design (MD)is a effective measures to improved the pcb equipment reliability. The system were made up simpleness functions of modules to reducing the complexity of the design. Both domestic and abroad, a large number of facts have proved this point, MD was a best choice for PCB equipment design....

Publisher: Everest PCB equipment Co.,Ltd

Void Detection in Large Solder Joints of Integrated Power Electronics

Dec 06, 2012 | Patrick Schuchardt

Inspection of integrated power electronics equals sophisticated test task. X-ray inspection based on 2D / 2.5D principles not utilizable. Full 3D inspection with adapted image capturing and reconstruction is necessary for test task.... First published in the 2012 IPC APEX EXPO technical conference proceedings. ...

Publisher: GOEPEL Electronic

Overcoming Logistic, Economic and Technical Challenges to Implementing Functional Test in High Mix / High Volume Production Environments

Nov 29, 2012 | Craig T. Pynn

First published in the 2012 IPC APEX EXPO technical conference proceedings... Functional circuit test (FCT) of circuit boards and end products in a high volume (>1000 units per day) production environment presents challenging technical, logistic and cost obstacles that are usually more complex than those encountered at the inspection (automated optical inspection) and the manufacturing process test step (in-circuit test)....

Publisher: SiFO Technologies

Effective Qualification of Soldering Iron Performance Criteria

Nov 27, 2012 | Metcal

Quality managers and line supervisors are routinely tasked with the responsibility of ensuring that the hand soldering process is under control. The method most commonly used is to measure the idle tip temperature of the soldering station and to use this reading as a benchmark of system compliance. This method, although popular is now being seriously questioned by many industry professionals as being irrelevant in qualifying true system process control.

This document aims to present a practical view of what factors are important for successful hand soldering and to suggest an alternative procedure for qualification that is simple, repeatable and directly related to the effectiveness of the soldering station....

Publisher: Metcal