Electronics Manufacturing Technical Articles

PCB Fabrication Processes and Their Effects on Fine Copper Barrel Cracks

Dec 23, 2015 | Edward Arthur, Charles Busa, Melissa Durfee, Chad Gibson, Wade Goldman P.E.; Raytheon Company, Space and Airborne Systems, The Charles Stark Draper Laboratory, Inc., Raytheon Company, Integrated Defense Systems.

The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.

The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias....

Publisher: Raytheon

Good Product Quality Comes From Good Design for Test Strategies

Dec 17, 2015 | Adrian Cheong

Product quality can be improved through proper application of design for test (DFT) strategies. With today's shrinking product sizes and increasing functionality, it is difficult to get good test coverage of loaded printed circuit boards due to the loss of test access. Advances in test techniques, such as boundary scan, help to recover this loss of test coverage. However, many of these test techniques need to be designed into the product to be effective.

This paper will discuss how to maximize the benefits of boundary scan test, including specific examples of how designers should select the right component, connect multiple boundary scan components in chains, add test access to the boundary scan TAP ports, etc. A discussion of DFT guidelines for PCB layout designers is also included. Finally, this paper will include a description of some advanced test methods used in in-circuit tests, such as vectorless test and special probing methods, which are implemented to improve test coverage on printed circuit boards with limited test access....

Publisher: Agilent Technologies, Inc.

Looking Forward - Manufacturing Execution Systems for SME’s

Dec 14, 2015 | Pete Doyon, VP Product Management, Schleuniger, Inc.

A Manufacturing Execution System (MES) is a software program that manages and monitors production work in a factory. The MES controls and monitors all manufacturing data in real time, so there is no guesswork as to the status of any given job, machine, operator, etc. The focus is on short-interval scheduling (shift or day) with an emphasis on optimizing the distribution of work orders. Larger manufacturers have employed MES’s for years but many small to medium sized enterprises (SME’s) have yet to adopt such systems. The benefits of using an MES are many. Looking forward, I predict that even the smallest manufacturing companies will employ MES systems in the future....

Publisher: Schleuniger, Inc.

Packaging Technology and Design Challenge for Fine Pitch Micro-Bump Cu-Pillar and BOT (Direct Bond on Substrate-Trace) Using TCNCP

Dec 02, 2015 | Myung-June Lee -Altera Corporation, SungSoon Park, DongSu Ryu, MinJae Lee - Amkor Technology, Hank Saiki, Seiji Mori, Makoto Nagai - NTK Technologies.

(Thermal Compression with Non-Conductive Paste Underfill) Method.

The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.

Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).

This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology....

Publisher: Altera Corporation

HCFC-225 Phaseout - What Now?

Dec 01, 2015 | Ed Kanegsberg

On January 1, 2015, nine months from APEX 2014, the production and use restrictions on HCFC-225 will be in effect throughout the United States. This phase out is encompassing in scope. This phase out will have significant technical, performance, and economic implications for the electronics industry. The regulatory situation remains fluid. A number of alternative solvents have been or are in the process of being developed. We discuss the options for assemblers and component manufacturers....

Publisher: BFK Solutions LLC

Study of Various PCBA Surface Finishes

Nov 25, 2015 | Georgie Thein, David Geiger, and Murad Kurwa.

In this study various printed circuit board surface finishes were evaluated, including: organic solderability preservative (OSP), plasma finish (PF), immersion silver (IAg), electroless nickel / immersion silver (ENIS), electroless nickel / immersion gold hi-phosphorus (ENIG Hi-P), and electroless nickel / electroless palladium / immersion gold (ENEPIG). To verify the performance of PF as a post-treatment option, it was added to IAg, ENIG Hi-P, and ENEPIG to compare with non-treated. A total of nine groups of PCB were evaluated. Each group contains 30 boards, with the exception on ENIS where only 8 boards were available....

Publisher: Flex (Flextronics International)

HALT Testing of Backward Soldered BGAs on a Military Product

Nov 19, 2015 | B. Gumpert, B. Fox, L. Woody

The move to lead free (Pb-free) electronics by the commercial industry has resulted in an increasing number of ball grid array components (BGAs) which are only available with Pb-free solder balls. The reliability of these devices is not well established when assembled using a standard tin-lead (SnPb) solder paste and reflow profile, known as a backward compatible process. Previous studies in processing mixed alloy solder joints have demonstrated the importance of using a reflow temperature high enough to achieve complete mixing of the SnPb solder paste with the Pb-free solder ball. Research has indicated that complete mixing can occur below the melting point of the Pb-free alloy and is dependent on a number of factors including solder ball composition, solder ball to solder paste ratio, and peak reflow times and temperatures. Increasing the lead content in the system enables full mixing of the solder joint with a reduced peak reflow temperature, however, previous research is conflicting regarding the effect that lead percentage has on solder joint reliability in this mixed alloy solder joint....

Publisher: Lockheed Martin Corporation

The Perfect Copper Surface

Nov 12, 2015 | Eric Stafstrom; Technic Inc, Garo Chehirian; Tech-Etch.

In order to provide the functionality in today’s electronics, printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces, this means no nodules, no pits, and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However, the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble, phosphorized, copper anodes introduce particulate and limits the ability to control plating distribution....

Publisher: Technic Inc.

Print Performance Studies Comparing Electroform and Laser-Cut Stencils

Nov 05, 2015 | Rachel Miller Short, William E. Coleman Ph.D.; Photo Stencil | Joseph Perault; Parmi.

There has been recent activity and interest in Laser-Cut Electroform blank foils as an alternative to normal Electroform stencils. The present study will investigate and compare the print performance in terms of % paste transfer as well the dispersion in paste transfer volume for a variety of Electroform and Laser-Cut stencils with and without post processing treatments. Side wall quality will also be investigated in detail. A Jabil solder paste qualification test board will be used as the PCB test vehicle....

Publisher: Photo Stencil LLC

Novel Approaches for Minimizing Pad Cratering

Oct 29, 2015 | Chen Xu, Yunhu Lin; Alcatel-Lucent, Yuan Zeng, Pericles A. Kondos; Unovis-Solutions.

With the electronic industry moving towards lead-free assembly, traditional SnPb-compatible laminates need to be replaced with lead-free compatible laminates that can withstand the higher reflow temperature required by lead-free solders. Lead-free compatible laminates with improved heat resistance have been developed to meet this challenge but they are typically more brittle than SnPb laminates causing some to be more susceptible to pad cratering. In this paper, two novel approaches for minimizing pad cratering will be discussed. Preliminary results which validate the two approaches will also be presented....

Publisher: Alcatel-Lucent