DSPIS - Serial Peripheral Interface - Slave

DSPIS - Serial Peripheral Interface - Slave Description:

Overview

The DSPIS is a fully configurable SPI ma slave device, designated to operate with passive devices like memories, LCD drivers etc. The DSPIS allows user to configure polarity and phase of serial clock signal SCK. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPIS data are simultaneously transmitted and received. The DSPIS system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. The DSPIS allows the SPI Master to communicate with passive devices. When transmission starts (SS Line goes low) the first portion of data is copied to the address register and then to the ADDRESS bus output, after transmission of the address the DSPIS generates the read signal (RD) and copy DATAI bus contents to the transmitter shift register, and prepare data to be exchanged with SPI Master. During the next data portion transmission DSPIS simultaneously transmits data out and in. When the first data portion is received the DSPIS asserts DATAO bus generates the write signal (WE), then increments ADDRESS bus performs a read operation and prepare another data portion to be exchanged with SPI master. Transmission is ended when the SS line goes high. The DSPIS is a technology independent design that can be implemented in a variety of process technologies. DSPIS is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
DSPIS is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
DSPIS is a technology independent design that can be implemented in a variety of process technologies.

Features

■ Full duplex synchronous serial data transfer
■ Slave operation
■ Automatic read and write operations
■ Automatic address incrementation after any data portion transfer
■ Configurable address and data length
■ Configurable SCK phase and polarity
■ Supports speeds up 1/4 of system clock
■ Simple interface allows easy connection to passive devices, and SPI Master
■ Four transfer formats supported
■ Simple interface allows easy connection to microcontrollers
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

Type - Soft  

Availability - now

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, MAX II, HardCopy, FLEX 10K, Cyclone II, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Virtex-4 FX, Spartan-3,