D16450 - Configurable UART

D16450 - Configurable UART Description:

Overview

The D16450 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C450. D16450 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16450 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16450 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency
The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16450 core implementation and verification are very simply, by eliminating a number of clock trees in complete system.

Features

■ Software compatible with 16450 UART
■ Configuration capability
■ Separate configurable BAUD clock line
■ Majority Voting Logic
■ Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
■ In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
■ Independently controlled transmit, receive, line status, and data set interrupts
■ False start bit detection
■ 16 bit programmable baud generator
■ MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
■ Fully programmable serial-interface characteristics:
■ 5-, 6-, 7-, or 8-bit characters
■ Even, odd, or no-parity bit generation and detection
■ 1-, 1½-, or 2-stop bit generation
■ Baud generation
■ Complete status reporting capabilities
■ Line break generation and detection. Internal diagnostic capabilities:
■ Loop-back controls for communications link fault isolation
■ Break, parity, overrun, framing error simulation
■ Technology independent HDL Source Code
■ Full prioritized interrupt system controls
■ Fully synthesizable static design with no internal tri-state buffers

Benefits

■ Rapid prototyping and time-to-market reduction
■ Design risk elimination
■ Development costs reduction
■ Full customization
■ Global sales network
■ Technology independence
■ Professional service
■ Getting a sillicon proven IP

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

Type - Soft  

Equivalent Part - TL16C450

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,