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PCB layer to layer registration

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#78096

PCB layer to layer registration | 6 July, 2017

Hello everyone, I was curious if anyone knows what criteria there is for layer to layer registration. I have looked at ipc-600 and 601 and have not found anything or am missing something. We had a small qty. of pcbs sent to a customer and some inner layers were shorting now we are very sensitive on our inspection of bare PCB and very sensitive when it LOOKS like layers are shifted. Any input would be helpful.

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#78098

PCB layer to layer registration | 6 July, 2017

Hi Jack,

Haven't you done 100% E-test? there is a registration tolerance. CCD+/-2mil, Manual+/-4mils according to our manufacturing capacitites.

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#78142

PCB layer to layer registration | 7 July, 2017

Our PCB supplier was supposed to be doing 100% ET but a few of his PCBs were not, and were not marked as tested, so now we are supersensitive. We received some PCBs from a new supplier and one of our inspectors noticed some shift. I was looking for some criteria from IPC or some other standard.

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