Flaky Capacitor

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We have a 0603 film chip capacitor defined by mfgr as "stack... - Jun 05, 2014 by SWAG

If your TAL is 90 sec, and the mfg spec is ">230C for max 30... - Jun 05, 2014 by isd.jww

Good observation. I don't believe so as we reach 225 C for ... - Jun 05, 2014 by SWAG

Can you see the flaking right out of the oven? ... - Jun 06, 2014 by isd.jww

Component manufacturers subject their lots to thermal / refl... - Jun 06, 2014 by SteveO

Yes, jsd.jwww it can be seen right after reflow. I read bac... - Jun 09, 2014 by SWAG

SWAG

#72203

Flaky Capacitor | 5 June, 2014

We have a 0603 film chip capacitor defined by mfgr as "stacked metallized PPS film as dielectric with simple mold-less construction" that shows surface flaking post reflow. Flakes are small - SMT dandruff you could say. (FYI we don't run "Head and Shoulders" in our wash system). Customer doesn't like it. Board tests fine. Processing temp. is 225 C max, TAL = 90 sec. Recommended max process temp from chip mfgr. is 260 C for 5 sec max and >230 C for 30 sec. max. We are not infringing on either limit. What can we do? Is this common? Is there accept/reject standards that I don't know about for something like this? Our customer HATES F.O.D. so that is likely why they are having issues with this.

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isd.jww

#72204

Flaky Capacitor | 5 June, 2014

If your TAL is 90 sec, and the mfg spec is ">230C for max 30 sec.". Isn't 225C close enough to 230C, so that you are effectively exceeding mfg spec by 60 sec.?

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SWAG

#72205

Flaky Capacitor | 5 June, 2014

Good observation. I don't believe so as we reach 225 C for just a moment. That is the peak temp that occurs in the TAL range. TAL was measured at temps > 183 C (leaded process).

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isd.jww

#72211

Flaky Capacitor | 6 June, 2014

Can you see the flaking right out of the oven?

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SteveO

#72215

Flaky Capacitor | 6 June, 2014

Component manufacturers subject their lots to thermal / reflow testing per IPC /JEDEC STD-020. This involves running the parts through an oven 3X with a peak above 260C. I am not certain if passives go through the same test (theoretically they should) but ultimately this is how they classify IC's as being able to withstand such temperatures. In this test, the temperature of 260C is actually measured on the package surface. So if your peak of 225C is based on the joint temperature at this 0603, the top of the part will likely be at a higher temp. This is how you might unknowingly be exceeding their limits.

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SWAG

#72221

Flaky Capacitor | 9 June, 2014

Yes, jsd.jwww it can be seen right after reflow. I read back thru the spec sheet and under "soldering conditions" is says "temp. at cap surface" so thanks, SteveO I think you hit the nail on the head and we'll have to revisit the profile and target the cap surface. I'll have to take a lood at that JEDEC standard, too. Thanks for the help!

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