What is the extent of Probe mark allowed on a assembled board ? Is there any related material on net or standard .Recently we had an issue where the ICT was done and the joints on which the pins were tested had dents on the joints due to probe mark .
I'm not aware of any such stipulation about witness [probe] marks for assembled boards, per se. Certainly, witness marks should not affect the intended performance of the assembly, you know, like damaging the solder connection or smudging solder material into the vicinity of a trace. So, where assembly requirements are stated to be specific to probing or not, there can be no damage to connections or connectors just like other damage from any other unspecified source.
Certainly, IC fab circles discuss witness marks widely. Board fab circles discuss witness marks much less than IC fab, but do address them in IPC-6012.
IPC-6012B, section 22.214.171.124.2 Round Surface Mount Lads (BGA Pads)"One electrical test probe "witness" mark is allowed within the pristine area for Class 1, 2, and 3."
Actually, if you experience lack of witness marks, you probably have a problem. Witness marks are OK and will not affect your assembly. I assume this is an SMT assembly we are talking about, in which case, this is what your test pads are for. You should have enough spring force to penetrate any contaminates left over from the production process such as flux residue (This can be real cumbersome when it comes to ICT). The trick is to find how much spring force is needed for your particular assembly, and this will depend on your process. Too low a force and you will have APC issues, too high, and this could lead to vacuum issues depending on how well your fixture is sealed (gasket fixtures that is). A word of note, a higher spring force will also cause the probes to migrate out of the sockets over time, faster than normal, due to the surface friction when the vacuum is release. I use witness marks as an indication of probe alignment, as well as proof of probe contact. Witness marks are good and are expected.
Dear Dave/pr/Reese, Thank you so much for the information and this will certainly help me to align on the query .Would like to know further :During Flying probe testing the vias are also observed that they have pin mark on the annular ring due to the testing .Are these also acceptable or any criterias are there .Please advise .
How deep is the indent? I would say as long as it is hitting nothing but net (the solder fill), your fine. Besides, you should notice indents on your solder fillets of components on the top-side as well. This is also expected and acceptable.