Industry News | 2023-02-13 15:24:20.0
From the show floor – where 375 exhibitors displayed a multitude of high-tech machinery and in some cases artificial intelligence – including cutting-edge assembly, testing and inspection equipment, software automation, laser systems, additive manufacturing and factory of the future technologies, to dozens of technical conference sessions and PD courses covering such hot-topic tracks as smart factories, PCB fabrication and materials and high-density interconnects, IPC APEX EXPO 2023 was fueled by the possibilities of new advances in electronics manufacturing.
Industry News | 2001-11-27 13:09:48.0
IPC has announced its tutorial and workshop schedule for IPC Printed Circuits Expo 2002. A total of 34 courses are scheduled, including 15 full-day tutorials on March 24-25, and 19 half-day workshops, which will take place on March 25 and 28.
Industry News | 2013-09-17 07:21:08.0
The world market for PCBs reached nearly $60 billion in 2012, with 1.7 percent real growth over 2011, according to IPC’s World PCB Production Report for the Year 2012.
Industry News | 2003-05-27 08:07:35.0
IPC announces the recent release of three diverse industry products.
Industry News | 2022-10-20 14:32:44.0
Full-auto SMT Production Line includes solder paste printer machine, SMT placement machine (upper surface electronic components), reflow soldering oven machine, plug-in, wave furnace, testing machine etc. The wide application of Full-auto SMT Production Line promotes the miniaturization and multi-function of electronic products, and provides conditions for mass production and low defect rate production.
Industry News | 2008-07-24 17:38:17.0
Scotts Valley, CA � 15 July, 2008 - Vertical Circuits, Inc.(VCI), a leading supplier of advanced 3D die-level interconnect solutions, today announced its recognition of Asymtek, a Nordson company (Nasdaq: NDSN) and leader in dispensing, coating and jetting technologies, as a �Partner in Innovation.� Asymtek's Axiom� automated dispensing system plays a key role in enabling the high-volume manufacturing capability for VCI's 3D vertical interconnect process.
Industry News | 2003-04-23 08:39:30.0
For their contributions to IPC and the electronics industry
Technical Library | 2019-02-06 22:02:08.0
The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods, with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired, testing a variety of laminate materials (standard volume production with UL approval, low loss, and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified, as well as possible correlations or relationships among these higher speed test methods.
Technical Library | 2021-12-21 23:01:30.0
High density PWB (printed wiring board) with microvia technology is required for implementation of high density and high I/O area array packages (AAP). COTS (commercial off-the-shelf) AAP packaging technologies in high reliability versions with 1.27 mm pitch are now being considered for use in a number of NASA systems including the Space Shuttle and Mars Rovers. NASA functional system designs are requiring ever more denser AAP packages and board features, making board microvia technology very attractive for effectively routing a large number of package inputs/outputs.
Technical Library | 2015-01-28 17:39:34.0
Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology.
