Technical Library | 2020-02-18 09:56:24.0
Glob Top, Dam and Fill & Flit Chip Underfill To protect PCBs from damaging outside influences, they are coated with a thin layer of casting resin or protective finish during the conformal coating process. In addition to sealing the entire circuit board, it is possible to pot only sections or individual components on the substrate. Different methods ranging from "glob top" to "dam and fill" and "flip chip underfill" have been developed for this purpose.
Technical Library | 2014-08-28 17:09:23.0
The fastest growing package types in the electronics industry today are Bottom Termination Components (BTCs). While the advantages of BTCs are well documented, they pose significant reliability challenges to users. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies. This is especially true for new component packaging like BTCs. Obtaining relevant information can be difficult since information is often segmented and the focus is on design opportunities not on reliability risks (...)Commonly used conformal coating and potting processes have resulted in shortened fatigue life under thermal cycling conditions. Why do conformal coating and potting reduce fatigue life? This paper details work undertaken to understand the mechanisms underlying this reduction. Verification and determination of mechanical properties of some common materials are performed and highlighted. Recommendations for material selection and housing design are also given.
Technical Library | 2022-01-26 15:22:33.0
Reliability of conformal coatings used to mitigate tin whisker growth depends on their ability to contain tin whiskers. Two key material properties required to assess the reliability of a polyurethane coating are documented experimentally: adhesion strength and puncture strength. A modified blister test using a predefined blister area is employed to assess the adhesion strength and a puncture test is employed to evaluate the puncture strength of the coating. After measuring the properties at time zero, the coatings are subjected to accelerated testing conditions (high temperature/humidity storage and temperature cycling) and the degradations of the coating properties are documented.
Technical Library | 2015-03-26 19:16:03.0
Nickel-palladium-gold-finished terminals are susceptible to creep corrosion. Excessive creep corrosion can result in device failure due to insulation resistance loss between adjacent terminals. The mixed flowing gas test has been demonstrated to produce creep corrosion on parts with nickel-palladium-gold finished terminals. Conformal coats are often used to protect printed wiring assemblies from failure due to moisture and corrosion. However, coating may not be sufficient to protect lead terminations from failure.In this study, acrylic, silicone, urethane, parylene, and atomic layer deposit (ALD) coatings were examined for their effectiveness at preventing corrosion of nickel-palladium-gold-finished terminals.
Technical Library | 2015-03-04 10:56:26.0
As the proliferation of modern day electronics continues to drive miniaturization and functionality, electronic designers/assemblers face the issue of environmental exposure and uncommon applications never previously contemplated. This reality, coupled with the goal of reducing the environmental and health implications of the production and disposal of these devices, has forced manufacturers to reconsider the materials used in production. Furthermore, the need to increase package density and reduce costs has led to the rapid deployment of leadless packages such as QFN, POP, LGA, and Micro-BGA. In many cases, the manufacturers of these devices will recommend the use of no clean fluxes due to concerns over the ability to consistently remove flux residues from under and around these devices. These concerns, along with the need to implement a tin whisker mitigation strategy and/or increase environmental tolerance, have led to the conundrum of applying conformal coating over no clean residues.
Technical Library | 2010-02-10 23:50:23.0
The electronics industry has recently undertaken the transition to lead-free processing as a direct consequence of the RoHS directive, which came into force in July 2006. However, this is unlikely to be the last transition required since the European Solvent Emissions Directive, 1999 is starting to be implemented and enforced by national governments. This is resulting in pressure on larger manufacturers, currently emitting more than 5 tonnes of solvent vapour per annum to take steps to limit and reduce their emissions.
Technical Library | 2020-01-01 17:06:52.0
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.
Technical Library | 2015-08-18 14:02:37.0
What is UV Curing? “Ultraviolet (UV) light is an electromagnetic radiation with a wavelength from 400 nm to 100 nm, shorter than that of visible light but longer than X-rays.” (Source: Wikipedia). Ultraviolet or UV curing is used to create a photochemical reaction using high intensity Ultraviolet (UV) energy or “light” to quickly dry inks, adhesives or conformal coatings. Most materials cure with a UV wavelength around 350 ~ 400nm although some materials require UVC energy near 255nm. There are many advantages to using UV curing over other traditional methods of curing. Not only will it increase production speed, it assists in creating a better bond, and improves scratch and solvent resistance. When compared to other methods of curing, UV curing generates a more reliable cured product at a much higher rate of production in a considerably shorter period of time.
Technical Library | 2017-12-11 22:31:06.0
Typical printed circuit board assemblies (PCBAs) processed by reflow, wave, or selective wave soldering were analysed for typical levels of process related residues, resulting from a specific or combination of soldering process. Typical solder flux residue distribution pattern, composition, and concentration are profiled and reported. Presence of localized flux residues were visualized using a commercial Residue RAT gel test and chemical structure was identified by FT-IR, while the concentration was measured using ion chromatography, and the electrical properties of the extracts were determined by measuring the leak current using a twin platinum electrode setup. Localized extraction of residue was carried out using a commercial C3 extraction system. Results clearly show that the amount and distribution of flux residues are a function of the soldering process, and the level can be reduced by an appropriate cleaning. Selective soldering process generates significantly higher levels of residues compared to the wave and reflow process. For conformal coated PCBAs, the contamination levels generated from the tested wave and selective soldering process are found to be enough to generate blisters under exposure to high humidity levels.
Technical Library | 2016-04-08 01:19:52.0
PCB assembly designs become more complex year-on-year, yet early-stage form/fit compliance verification of all designed-in components to the intended manufacturing processes remains a challenge. So long as librarians at the design and manufacturing levels continue to maintain their own local standards for component representation, there is no common representation in the design-to-manufacturing phase of the product lifecycle that can provide the basis for transfer of manufacturing process rules to the design level. A comprehensive methodology must be implemented for all component types, not just the minority which happen to conform to formal packaging standards, to successfully left-shift assembly and test DFM analysis to the design level and thus compress NPI cycle times.(...)This paper will demonstrate the technological components of the working solution: the logic for deriving repeatable and standardized package and pin classifications from a common source of component physical-model content, the method for associating DFA and DFT rules to those classifications, and the transfer of those rules to separate DFM and NPI analysis tools elsewhere in the design-through-manufacturing chain resulting in a consistent DFM process across multiple design and manufacturing organizations.
