Technical Library | 2017-10-19 01:17:56.0
Wetting balance testing has been an industry standard for evaluating the solderability of surface finishes on printed circuit boards (PCB) for many years. A Wetting Balance Curve showing Force as a function of Time, along with the individual data outputs "Time to Zero" T(0), "Time to Two-Thirds Maximum Force" T(2/3), and "Maximum Force" F(max) are usually used to evaluate the solderability performance of various surface finishes. While a visual interpretation of the full curve is a quick way to compare various test results, this method is subjective and does not lend itself readily to a rigorous statistical evaluation. Therefore, very often, when a statistical evaluation is desired for comparing the solderability between different surface finishes or different test conditions, one of the individual parameters is chosen for convenience. However, focusing on a single output usually doesn't provide a complete picture of the solderability of the surface finish being evaluated.In this paper, various models here-in labeled as "point" and "area" models are generated using the three most commonly evaluated individual outputs T(0), T(2/3), and F(max). These models have been studied to quantify how well each describes the full wetting balance curve. The solderability score (S-Score) with ranking from 0 to 10 were given to quantify the wetting balance curve as the result of the model study, which corresponds well with experimental results.
Technical Library | 2018-03-28 14:54:36.0
Six decades of legacy experience makes the specification and production of screens and masks to produce repeatable precision results mostly an exercise in matching engineering needs with known ink and substrate performance to specify screen and stencil characteristics. New types of functional and electronic devices, flex circuits and medical sensors, industrial printing, ever finer circuit pitch, downstream additive manufacturing processes coupled with new substrates and inks that are not optimized for the rheological, mechanical and chemical characteristics for the screen printing process are becoming a customer driven norm. Many of these materials do not work within legacy screen making, curing or press set-up parameters. Many new materials and end uses require new screen specifications.This case study presents a DOE based method to pre-test new materials to categorize ink and substrate rheology, compatibility and printed feature requirement to allow more accurate screen recipes and on-press setting expectations before the project enters the production environment where time and materials are most costly and on-press adjustment methods may be constrained by locked, documented or regulatory processes, equipment limitations and employee experience.
Technical Library | 2018-04-18 23:55:01.0
Higher functionality, higher performance and higher reliability with smaller real estate are the mantras of any electronic device and the future guarantees more of the same. In order to achieve the requirements of these devices, designs must incorporate fine line and via pitch while maintain good circuitry adhesion at a smooth plating-resin interface to improve signal integrity. The Semi-Additive Process (SAP) is a production-proven method used on low dielectric loss tangent (Df) build-up materials that enables the manufacture of ultra-fine circuitry. (...) This paper will discuss a new SAP process for low loss build-up materials with low desmear roughness (Ra= 40-100 nm) and excellent adhesion (610-680 gf/cm) at various processing conditions. Along with the process flow, the current work will also present results and a discussion regarding characterization on the morphology and composition of resin and/or metal plating surfaces using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX), surface roughness analysis, plating-resin adhesion evaluation from 90o peel tests
Technical Library | 2020-11-04 17:57:41.0
Residues present on circuit boards can cause leakage currents if not controlled and monitored. How "Clean is Clean" is neither easy nor cheap to determine. Most OEMs use analytical methods to assess the risk of harmful residues. The levels that can be associated with clean or dirty are typically determined based on the exposed environment where the part will be deployed. What is acceptably clean for one segment of the industry may be unacceptable for more demanding segments. As circuit assemblies increase in density, understanding cleanliness data becomes more challenging. The risk of premature failure or improper function is typically site specific. The problem is that most do not know how to measure or define cleanliness nor can they recognize process problems related to residues. A new site specific method has been designed to run performance qualifications on boards built with specific soldering materials, reflow settings and cleaning methods. High impedance measurements are performed on break off coupons designed with components geometries used to build the assembly. The test method provides a gauge of potential contamination sources coming from the assembly process that can contribute to electrochemical migration.
Technical Library | 2019-10-24 06:29:59.0
Making your novel electronic item design ready for mass fabrication and printed circuit board assembly consists of a lot of steps as well as risks. I will provide a few recommendations about how to neglect pricey errors and how to reduce the time to promote your novel item designs. You can hire printed circuit board assembly services for this. As soon as you have accomplished your product as well as printed circuit board design, you wish to get started developing prototypes prior to you commit to big fabrication volume. A lot of design software packages, for instance, PCB layout design software, as well as an industrial design software program, possess simulation potentials incorporated. Carrying out a simulation facilitates curtailing numerous design mistakes prior to the first prototype is developed. In case you are developing an intrusive item, you might desire to think about a modular design wherein all of the chief functionalities are situated in individual modules. All through your testing, you could then swap modules that don’t cater to the design limits. Spinning individual modules would be swifter and more cost-effective in comparison to spinning a complete design. Counting on the design intricacy, you can mull over manually mounting printed circuit board elements to bank dollars. Nonetheless, for medium to big intricacy this procedure likely to be very time taking, typically in case you wish to create numerous prototypes. Hence it makes sense thinking about a contract manufacturer for the assembly. Whilst running miniature quantity fabrication runs, the fabrication setup expenditure will usually control the by and large prototype constructs expenditure. Whilst seeking a subcontractor, it is finest to choose a vendor that focuses on prototype builds to reduce the cost. Prototype printed circuit board fabricators characteristically join the circuit boards of a number of clients which efficiently shares the setup expenditure in the midst of some customers. The disadvantage is that you would characteristically only be able to want among numerous standard printed circuit board material thicknesses as well as sizes. Apart from choosing a supplier with low setup expenditure, choosing a firm that would moreover be capable to manage your whole fabrication runs curtails mistakes because switching fabricators have the chance of errors owing to a specific supplier interpreting fabrication design data in a different way. This manner your design is already translated into the particular machine data that implies little or no setup expenditure for your final fabrication. A few PCB manufacturers also provide printed circuit board design services that are awesome plus if you do not possess experience with the design. Moreover, these vendors would be capable to help you in case there are issues with your design folders and be capable to detect issues prior to the fabrication.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
Technical Library | 2022-10-11 20:29:31.0
Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantiication of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.
