Electronics Forum | Thu Oct 30 15:36:18 EDT 2008 | grantp
Hi, Sounds like your engineer does not know what he's doing. We have developed and built hundreds of thousands of boards with normal square pads for 0402, and we just use a 5 thou stencil with 5% reduction and it works well. Decoupling? What is tha
Electronics Forum | Fri Jan 21 13:25:33 EST 2000 | Dennis _F
Im attempting to start a data base relating to stencil aperture reduction relationship to package types.Does anyone here have anything as such they would be willing to share? My direct Email is dennis.fowler@vmic.com Thanks in advance.
Electronics Forum | Mon Dec 20 04:14:06 EST 1999 | Wolfgang Busko
Oh yes, that�s the thing with the PCB houses, always doing such things with our precious data and or wishes of the ideal paddesign. Without any aperture reduction we would have enough troubles with the PCB�s we mostly get. Wolfgang
Electronics Forum | Thu Jun 26 21:40:09 EDT 2003 | Dreamsniper
FP shouldn't be a problem I should say..Typo error. regards,
Electronics Forum | Wed Dec 15 09:18:00 EST 1999 | Chris May
Can people let me know what reductions are typical for stencils. This can obviously be affected by the technology of the board, but for chip caps and R's do you use 1:1 and only reduce for finer pitch stuff ? Your help would be appreciated. Regards
Electronics Forum | Fri Jun 27 08:32:08 EDT 2003 | davef
You should be fine. A fifteen percent reduction of these pads will probably improve reliability, depending on spacing of course.
Electronics Forum | Mon Sep 20 20:51:36 EDT 1999 | Greg H.
My stencil thickness is 6 mil and we got qfp's with fine pitch. how many percent should i reduce my stencil aperture using a 6 mil stencil for 0.5 mm pitch and 0.4 mm pitch ? thanks
Electronics Forum | Thu Aug 20 19:07:29 EDT 2009 | smt_guy
reduce the stencil aperture to prevent tombstoning in vapor phase process. from my experience a 6 mil thick must be at least between 20 to 30 % aperture reduction for 0805's and below. cheers!
Electronics Forum | Tue Feb 08 10:33:26 EST 2005 | Dougs
have you had any reduction in aperture size though, we generally use a 6 mil stencil thickness with a 10% aperture size reduction for chip components and leaded components ( SOIC - QFP ) and a 1:1 ratio for BGA components without any problems.
Electronics Forum | Fri Dec 17 01:21:54 EST 1999 | Victor Salazar
Weare using a Home plate design on 1210 or larger, 20% reduction on pkgs from 1206 to 1210, 10% reduction on 1206 or smaller, 0 reduction on all leaded components(sot-23, IC's) with a 6 mil stencil. For fine pitch we are using 4mil stencils. We h
