Electronics Forum | Mon Feb 21 11:22:21 EST 2000 | K. Ckak
Hi Kurt, I agree with Dave F. I had exact same problem with PBGA placement. We requested our PCB vendor to plug/tent via (button printing) after HASL with SR1000 which worked well in the long run. There are couple of failure modes associated wit
Electronics Forum | Mon Jun 18 18:14:59 EDT 2001 | davef
Would comment extensively on the following? The time is a fact for X-ray inspection. If you set the contrast, tilting angle correctly (provide you did enough cross section to know the few type of failure mode: e.g. smaller balls, shorts, missing on
Electronics Forum | Wed May 01 12:05:44 EDT 2002 | peterson
FMEA, when used correctly, is an excellent tool. The best thing about it is that it holds INDIVIDUALS accountable. The meeting cannot be closed until specific people (usually process types like me!) are assigned specific duties. I agree with Dave tha
Electronics Forum | Wed Oct 05 15:03:40 EDT 2005 | Amol
depends on what you want evaluated! you can thermal cycle the BGAs and the examine the x-sections to determine failure modes at different stages of thermal cycles. you can do a stress test and corelate the # of thermal cycles with the microstructu
Electronics Forum | Tue Apr 13 08:21:05 EDT 2010 | esca
Hi manchella, After ATC test, two different failure modes can be present: solder FATIGUE (into bulk) or BRITTLE INTERMETALLIC fracture. So, first you have to verify this. Moreover, which brand of SMT paste have you used ? The crack into solder joint
Electronics Forum | Tue Sep 05 14:31:42 EDT 2017 | rgduval
Create a package, set the mechanical centering to the dimensions of the 8-DFN that you're trying to place, test the centering. Tweak the dimension that's failing. Shouldn't be too much of a problem. An 8-DFN package is nothing more than a rectangu
Electronics Forum | Mon Feb 21 21:28:13 EST 2005 | abhirami
Davef, We see increased IMC thickness for electroless Ni and the brittle mode failure occurs much earlier in multiple reflows, exposing IMC layers. Not good for board level reliability.Regards. GV
Electronics Forum | Wed Oct 28 23:01:57 EST 1998 | Dave F
| I would like to know if there are any standard guidelines for the development of Process Failure Mode and Effect Analysis. If there is can you refer me to the source. | | I would also like to be referred to any source relating to current developme
Electronics Forum | Fri Apr 27 13:41:19 EDT 2001 | 061032
The "band wagon" was a corporate decision. The performance issue concerned a communications problem between the line computer and the F5 (f5 locked up in the middle of a PCB). This issue did not show it's ugly head until a month after install. I t
Electronics Forum | Fri Apr 11 11:26:09 EDT 2003 | Brian W.
Cracked capacitors usually are not found at ICT. Unless the cap is completely cracked, the capacitance may not change much, and the usual failure mode is a leakage current. This is usually only seen in ESS type testing, when temperature and humidit
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