Technical Library | 2020-07-02 01:14:44.0
Head-in-Pillow (HIP) defects are a growing concern in the electronics industry. These defects are usually believed to be the result of several factors, individually or in combination. Some of the major contributing factors include: surface quality of the BGA spheres, activity of the paste flux, improper placement / misalignment of the components, a non-optimal reflow profile, and warpage of the components. To understand the role of each of these factors in producing head-in-pillow defects and to find ways to mitigate them, we have developed two in-house tests.
Technical Library | 2014-08-19 16:04:28.0
SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller, with denser interconnect arrays, and processes such package-on-package assembly become prevalent, advanced methods using dual surface full-field data become critical for effective Assembly Planning, Quality Assurance, and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required, to effectively address the challenges of modern SMT assembly.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2023-09-05 21:00:53.0
The head on pillow defect is becoming more common. This paper describes one such occurrence for an OEM and explains how it was dealt with. In this particular case it was solved by application of problem solving skills by the OEM, component supplier and the solder paste provider
Technical Library | 2014-12-18 17:22:34.0
Manufacturing technology faces challenges with new packages/process when confronting the need for high yields. Identifying product defects associated with the manufacturing process is a critical part of electronics manufacturing. In this project, we focus on how to use AXI to identify BGA Head-in-Pillow (HIP), which is challenging for AXI testing. Our goal is to help us understand the capabilities of current AXI machines.
Technical Library | 2010-03-04 18:11:53.0
While the electronics manufacturing industry has been occupied with the challenge of RoHS compliance and with it, Pb-free soldering, established trends of increasing functionality and miniaturization have continued. The increasing use of ultra-fine pitch and area-array devices presents challenges in both printing and flux technology. With the decrease in both the size and the pitch of said components, new problems may arise, such as head-in-pillow and graping defects
Technical Library | 2016-05-13 11:44:16.0
The process of manufacturing and qualifying IC's consists of many steps while Temperature forcing systems play a crucial role in the final testing process. These environmental tests assure quality and reliability by stressing the device on one hand as well as helping to characterize and validate it on the other hand (making sure manufacturing outcome meets the design requirements). At later stages the temperature testing can support failure analysis effort and root cause analysis. AS common practice we are dealing with few different kinds of temperature forcing systems: Chambers, Thermal Stream systems and Direct Thermal Head systems. In this article I would like to focus on the practical aspects of utilizing Thermal Stream systems and Direct Thermal Head systems.
Technical Library | 2023-11-20 17:30:11.0
Summary for today 1. Electronic component inspection and failure analysis. 2. Component counting and material management. 3. Reverse engineering. 4. Counterfeit detection. 5. Real-time defect verification. 6. Computed tomography (CT) techniques and how to differentiate between 2D, 2.5D, and 3D x-ray inspection. 7. Design for manufacturing (DFM) and design for x-ray inspection (DFXI). 8. Voids, bridging, and head-in-pillow failures in bottom terminated components (BTC). 9. Artificial Intelligence and x-ray inspection
Technical Library | 2021-08-25 16:34:37.0
As the traditional eutectic SnPb solder alloy has been outlawed, the electronic industry has almost completely transitioned to the lead-free solder alloys. The conventional SAC305 solder alloy used in lead-free electronic assembly has a high melting and processing temperature with a typical peak reflow temperature of 245ºC which is almost 30ºC higher than traditional eutectic SnPb reflow profile. Some of the drawbacks of this high melting and processing temperatures are yield loss due to component warpage which has an impact on solder joint formation like bridging, open defects, head on pillow.
Technical Library | 2023-11-20 18:10:20.0
The electronics production is prone to a multitude of possible failures along the production process. Therefore, the manufacturing process of surface-mounted electronics devices (SMD) includes visual quality inspection processes for defect detection. The detection of certain error patterns like solder voids and head in pillow defects require radioscopic inspection. These high-end inspection machines, like the X-ray inspection, rely on static checking routines, programmed manually by the expert user of the machine, to verify the quality. The utilization of the implicit knowledge of domain expert(s), based on soldering guidelines, allows the evaluation of the quality. The distinctive dependence on the individual qualification significantly influences false call rates of the inbuilt computer vision routines. In this contribution, we present a novel framework for the automatic solder joint classification based on Convolutional Neural Networks (CNN), flexibly reclassifying insufficient X-ray inspection results. We utilize existing deep learning network architectures for a region of interest detection on 2D grayscale images. The comparison with product-related meta-data ensures the presence of relevant areas and results in a subsequent classification based on a CNN. Subsequent data augmentation ensures sufficient input features. The results indicate a significant reduction of the false call rate compared to commercial X-ray machines, combined with reduced product-related optimization iterations.
