Technical Library | 2019-09-03 17:06:09.0
Both optical and scanning electron microscopy (SEM) are powerful tools for failure analysis in electronics and are used for low and high magnification examination. This article will provide detailed, step by step information for examining solder joints.
Technical Library | 2021-03-10 23:57:29.0
Latent short circuit failures have been observed during testing of Printed Circuit Boards (PCB) for power distribution of spacecraft of the European Space Agency. Root cause analysis indicates that foreign fibers may have contaminated the PCB laminate. These fibers can provide a pathway for electromigration if they bridge the clearance between nets of different potential in the presence of humidity attracted by the hygroscopic laminate resin. PCB manufacturers report poor yield caused by contamination embedded in laminate. Inspections show ...
Technical Library | 2023-01-10 20:08:36.0
Nickel corrosion in ENIG and ENEPIG is occasionally reported; when encountered at assembly it manifests as soldering failures in ENIG and wire bond lifts in ENEPIG. Although not common, it can be highly disruptive, resulting in missed deliver schedules, supply chain disruption, failure analysis investigations, and liability - all very costly.
Technical Library | 2019-01-02 21:51:49.0
Failed solder joints remain a constant source of printed circuit board failure. Soldering is the bonding of metallic surfaces via an intermetallic compound (IMC). The interaction between thermal energy delivery, flux chemistry, and solder chemistry creates the solder bond or joint. Today, reliability relies on visual inspection; operator experience and skill, control of influencers e.g. tip geometry, tip temperature, and collection and analysis of process data. Each factor involved with the formation of the solder joint is an element of risk and can affect either throughput or repeatability. Mitigating this risk in hand soldering requires the identification of these factors and a means to address them.
Technical Library | 2009-04-30 18:06:24.0
This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials, and peak temperatures on the above. The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored.
Technical Library | 2016-05-13 11:44:16.0
The process of manufacturing and qualifying IC's consists of many steps while Temperature forcing systems play a crucial role in the final testing process. These environmental tests assure quality and reliability by stressing the device on one hand as well as helping to characterize and validate it on the other hand (making sure manufacturing outcome meets the design requirements). At later stages the temperature testing can support failure analysis effort and root cause analysis. AS common practice we are dealing with few different kinds of temperature forcing systems: Chambers, Thermal Stream systems and Direct Thermal Head systems. In this article I would like to focus on the practical aspects of utilizing Thermal Stream systems and Direct Thermal Head systems.
Technical Library | 1999-08-05 10:27:43.0
This document is an update to the 1994 Quality and Reliability Roadmap issued in support of the 1994 National Technology Roadmap for Semiconductors. This report revisits the challenges, constraints, priorities, and research needs pertaining to quality and reliability issues. It also provides key project proposals that must be implemented to address concerns about reliability attainment and defect learning. An expanded section on test-to-test, diagnostics, and failure analysis; an edited version of the Product Analysis Forum Roadmap; and an appendix containing a draft report highlighting reliability issues is included.
Technical Library | 2014-06-12 16:40:19.0
Occurrence of popcorn in IC packages while assembling them onto the PCB is a well known moisture sensitive reliability issues, especially for surface mount packages. Commonly reflow soldering simulation process is conducted to assess the impact of assembling IC package onto PCB. A strain gauge-based instrumentation is developed to investigate the popcorn effect in surface mount packages during reflow soldering process. The instrument is capable of providing real-time quantitative information of the occurrence popcorn phenomenon in IC packages. It is found that the popcorn occur temperatures between 218 to 241°C depending on moisture soak condition, but not at the peak temperature of the reflow process. The presence of popcorn and delamination are further confirmed by scanning acoustic tomography as a failure analysis.
WASET - World Academy of Science, Engineering and Technology
Technical Library | 2020-10-27 02:07:31.0
For companies that choose to take the Pb-free exemption under the European Union's RoHS Directive and continue to manufacture tin-lead (Sn-Pb) electronic products, there is a growing concern about the lack of Sn-Pb ball grid array (BGA) components. Many companies are compelled to use the Pb-free Sn-Ag-Cu (SAC) BGA components in a Sn-Pb process, for which the assembly process and solder joint reliability have not yet been fully characterized. A careful experimental investigation was undertaken to evaluate the reliability of solder joints of SAC BGA components formed using Sn-Pb solder paste. This evaluation specifically looked at the impact of package size, solder ball volume, printed circuit board (PCB) surface finish, time above liquidus and peak temperature on reliability. Four different BGA package sizes (ranging from 8 to 45 mm2) were selected with ball-to-ball pitch size ranging from 0.5mm to 1.27mm. Two different PCB finishes were used: electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) on copper. Four different profiles were developed with the maximum peak temperatures of 210oC and 215oC and time above liquidus ranging from 60 to 120 seconds using Sn-Pb paste. One profile was generated for a lead-free control. A total of 60 boards were assembled. Some of the boards were subjected to an as assembled analysis while others were subjected to an accelerated thermal cycling (ATC) test in the temperature range of -40oC to 125oC for a maximum of 3500 cycles in accordance with IPC 9701A standard. Weibull plots were created and failure analysis performed. Analysis of as-assembled solder joints revealed that for a time above liquidus of 120 seconds and below, the degree of mixing between the BGA SAC ball alloy and the Sn-Pb solder paste was less than 100 percent for packages with a ball pitch of 0.8mm or greater. Depending on package size, the peak reflow temperature was observed to have a significant impact on the solder joint microstructural homogeneity. The influence of reflow process parameters on solder joint reliability was clearly manifested in the Weibull plots. This paper provides a discussion of the impact of various profiles' characteristics on the extent of mixing between SAC and Sn-Pb solder alloys and the associated thermal cyclic fatigue performance.
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