Electronics Forum | Fri Sep 30 19:14:35 EDT 2005 | DasonC
The stencil is 5 mil thick and the aperture is 12 mil sq. We found open but can't detect by x-ray. The process which we are using is no clean TIN/LEAD. Just thinking the ball size variance from 0.35~0.45mm per IPC-7095, in worst case scenarios, th
Electronics Forum | Fri May 26 05:54:40 EDT 2000 | Sal
For the past year now we have been printing adhesive with no real problems. Our printing ranges from 0603's to SOIC using a variation of aperture sizes and metal thickness foils. The crucial parameters are : aperture sizes : These obviously depend o
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
Technical Library | 2014-03-13 15:25:01.0
A student competition paper at Budapest University of Technology And Economics, Department of Electronics Technology gives background, covers stencil design and discusses stencils intended for pin in paste application. The stencil applied for depositing the solder paste is a thin, 75–200 µm thick metal foil, on which apertures are formed according to the solder pads on the printed circuit board. Stencil printing provides a fast, mass solder paste deposition process; relatively expensive, appropriate and recommended for mass production.
SMTnet Express, September 27, 2018, Subscribers: 31,354, Companies: 11,055, Users: 25,237 Assessing the Effectiveness of I/O Stencil Aperture Modifications on BTC Void Reduction Carlos Tafoya, Gustavo Ramirez, Timothy O'Neill; AIM Solder Bottom
SMTnet Express, March 13, 2014, Subscribers: 22531, Members: Companies: 13818, Users: 35857 Stencil Design Guidelines for Electronics Assembly Technologies Oliver Krammer; Budapest University of Technology and Economics. A student competition
