Technical Library | 2016-04-08 01:19:52.0
PCB assembly designs become more complex year-on-year, yet early-stage form/fit compliance verification of all designed-in components to the intended manufacturing processes remains a challenge. So long as librarians at the design and manufacturing levels continue to maintain their own local standards for component representation, there is no common representation in the design-to-manufacturing phase of the product lifecycle that can provide the basis for transfer of manufacturing process rules to the design level. A comprehensive methodology must be implemented for all component types, not just the minority which happen to conform to formal packaging standards, to successfully left-shift assembly and test DFM analysis to the design level and thus compress NPI cycle times.(...)This paper will demonstrate the technological components of the working solution: the logic for deriving repeatable and standardized package and pin classifications from a common source of component physical-model content, the method for associating DFA and DFT rules to those classifications, and the transfer of those rules to separate DFM and NPI analysis tools elsewhere in the design-through-manufacturing chain resulting in a consistent DFM process across multiple design and manufacturing organizations.
Technical Library | 2018-04-25 15:54:52.0
An automotive wire harness rarely has just a single part number that can be ordered and installed in a vehicle. Typically, there are many different versions of the same harness based on the orderable content in the vehicle. These versions (often called harness levels) will have unique part numbers. The quantity of these levels and their content is what is typically called complexity and it has a significant impact on the cost of the harness.Quantifying these costs is often very difficult especially with manual methods of deriving and costing the complexity solution. Therefore, traditionally, harness costing has focused on the piece cost of each harness level. When these complexity related costs are considered it is typically with overly simplified cost modeling techniques.This paper will focus on the quantification of these complexity related costs so that they can be modeled allowing automated algorithms to optimize for these costs. A number of real world examples will be provided as well. Since no two businesses are alike, it is the aim of this paper to provide the foundational knowledge and methodology so the reader can assess their own business to model how variation complexity costs affect their business.
Technical Library | 2022-09-12 14:07:47.0
Unique component handling issues can arise when an assembly factory uses highly-moisture sensitive surface mount devices (SMDs). This work describes how the distribution of moisture within the molded plastic body of a SMD is an important variable for survivability. JEDEC/IPC [1] moisture level rated packages classified as Levels 4-5a are shown to require additional handling constraints beyond the typical out-of-bag exposure time tracking. Nitrogen or desiccated cabinet containment is shown as a safe and effective means for long-term storage provided the effects of prior out-of-bag exposure conditions are taken into account. Moisture diffusion analyses coupled with experimental verification studies show that time in storage is as important a variable as floor-life exposure for highly-moisture sensitive devices. Improvements in floor-life survivability can be obtained by a handling procedure that includes cyclic storage in low humidity containment. SMDs that have exceeded their floor-life limits are analyzed for proper baking schedules. Optimized baking schedules can be adopted depending on a knowledge of the exposure conditions and the moisture sensitivity level of the device.
Technical Library | 2016-09-08 16:27:49.0
In this investigation a test matrix was completed utilizing 900 electrodes (small circuit board with parallel copper traces on FR-4 with LPI soldermask at 6, 10 and 50 mil spacing): 12 ionic contaminants were applied in five concentrations to three different spaced electrodes with five replicas each (three different bare copper trace spacing / five replications of each with five levels of ionic concentration). The investigation was to assess the electrical response under controlled heat and humidity conditions of the known applied contamination to electrodes, using the IPC SIR (surface insulation resistance) J-STD 001 limits and determine at what level of contamination and spacing the ionic / organic residue has a failing effect on SIR.
Technical Library | 2016-02-04 19:11:47.0
In a typical mechatronic manufacturing functional test setup, actual load simulations are usually done by connecting the DUT outputs to power or ground in order to establish either a high or low side driver. Each output is connected with different load and the test will either be sequential or concurrent. At lower power levels, these can usually be managed with general purpose switches. However, when it comes to higher power levels of currents more than 5 amps, such switching and loading might pose a greater challenge. Furthermore, critically in the manufacturing line, the tradeoff between cost and test time would have a great influence on the test strategy.This paper will present some key points to design a cost effective high power switching and load management solution.
Technical Library | 2021-04-21 15:10:16.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness. Due to the various advantages they offer, the use of Ball Grid Array packages is common across all industry sectors. They are also prone to process voiding issues. This study was performed to determine if vacuum assisted reflow process can help alleviate the voids in area array solder joints. Test parameters in this study largely focused on vacuum pressure level and vacuum dwell time.
Technical Library | 2022-10-31 18:35:40.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness. Due to the various advantages they offer, the use of Ball Grid Array packages is common across all industry sectors. They are also prone to process voiding issues. This study was performed to determine if vacuum assisted reflow process can help alleviate the voids in area array solder joints. Test parameters in this study largely focused on vacuum pressure level and vacuum dwell time.
Technical Library | 2023-02-13 18:56:42.0
This paper describes the results of an intensive whisker formation study on Pb-free assemblies with different levels of cleanliness. Thirteen types of as-received surface-mount and pin-through-hole components were cleaned and intentionally contaminated with solutions containing chloride, sulfate, bromide, and nitrate. Then the parts were assembled on double-sided boards that were also cleaned or intentionally contaminated with three fluxes having different halide contents. The assemblies were subjected to high-temperature/high-humidity testing (85_C/85% RH). Periodic examination found that contamination triggered whisker formation on both exposed tin and solder fillets. Whisker occurrence and parameters depending on the type and level of contamination are discussed. Cross-sections were used to assess the metallurgical aspects of whisker formation and the microstructural changes occurring during corrosion.
Technical Library | 2010-09-02 13:13:03.0
As chip packaging and interconnectivity have become more dense and operate at higher clock frequencies, physical access for traditional bed-of-nails testing becomes limited. This results in loss of ICT (in-circuit test) fault coverage and higher test fi
Technical Library | 2020-02-05 18:20:06.0
Consortium Projects - Thermal Cycling Reliability Consortium projects allow for joint research to investigate the reliability of multiple solder alloys under a variety of environmental stress conditions. Project jointly sponsored by iNEMI and HDP User Group and including CALCE and Universal consortium currently assessing 15 third-generation solder alloys..
