Electronics Forum | Mon Aug 30 10:17:16 EDT 2010 | markgray
We currently use this devise in one of our designs with no issues. We are using a 3mil stencil and a 45% apperature reduction. It is virtually impossible to eliminate voids but they are in an acceptable range. Solder balls are caused on this componen
Electronics Forum | Wed Aug 26 12:06:44 EDT 2009 | clampron
Good Morning, I have been struggling with this part for some time now. I have to agree that whoever designed this part, did not have to manufacture with it. We have advanced to a point where they have a acceptable yield but I believe that will be hi
Electronics Forum | Mon Apr 27 19:31:12 EDT 2009 | stevek
Remember that the 25% is a reduction in cross sectional area. A void in the middle of the ball that reduces the cross sectional area by 25% is about half the diameter of the ball. If it is closer to either termination, the corresponding size would
Electronics Forum | Wed May 22 19:10:47 EDT 2013 | anvil1021
We do a lot of these devices and I guess I am not familiar the term "Dry Solder". The QFN device is not designed to have a drain hole, but needs to have thermal vias to control heat in most cases. We have used every possible gnd pad design and modifi
Electronics Forum | Wed Sep 01 06:18:05 EDT 2010 | grahamcooper22
Dear SMT Manufacturer, As moisture is eliminated as the cause then solder paste volume will probably be the main contributing factor. More paste means more chance of solder balls and more flux fumes that need to be evaporated to reduce voiding. Even
Electronics Forum | Thu Mar 30 21:46:56 EST 2000 | Dave F
Reg: This is copy / paste from draft version of IPC 7095 ( issued May 1999 ) ... 7.3 Assembly accept/reject criteria 7.3.1 Voids in solder joint a. Sources of Voids There can be voids in solder balls, or at the solder joints to the BGA, or at the so
Electronics Forum | Tue Apr 29 11:19:09 EDT 2003 | davef
Metallization failure. A defect such as voids, cracks, separations, depressions, notches or tunnels or any combination in the cross sectional reduction that is a basis for rejection.
Electronics Forum | Sat May 30 01:31:49 EDT 2009 | mika
make 4 square rounded corner apertures on the ground pad and the total reduction of 20 % (80 % solder paste). Then you still be able to solder the terminals around. Don't worry to much of the void's. Just following my tips and you will be fine. The
Electronics Forum | Fri Mar 04 18:28:21 EST 2011 | hegemon
First, I would inspect for lack of solder bridges from the center slug to the outside leads. I would then look for evidence that the solder paste has reflowed beneath the component, without leaving too much void percentage. Typically we allow up
Electronics Forum | Fri Jul 20 13:50:22 EDT 2018 | vchauhan
This question is regarding stencil design: I am having voids under QFN TI P/N LMZ20502SILT. I have attached component pic. Signal pin is 18X16 mils. Center pads are 31 mil sq. Initially I had stencil done with one mil per side reduction on signal pad
