This paper presents the results of a joint - three way study between Amkor Technology, Panasonic Factory Solutions and Spansion in the area of package on package (PoP) board level reliability (BLR) (...) The scope of this paper is to cover the already popular 14 x 14mm PoP package size that provides a 152 pin stacked interface which supports a high level of flexibility in the memory architecture for multimedia requirements.
Ball Grid Array devices, BGAs, are widely used in a vast range of products including consumer, telecommunications and office based systems. As an area array device of solder joints, it provides high packing density with a relatively easy introduction cycle. However, over the last couple of years engineers have started to experiment, and in some cases implement, stacked packages, of the type often called Package on Package, or POP. In simple terms, POP devices are the stacking of components, one on top of the other, either during the original component manufacture or during printed board assembly.
As a part of series of studies on X-Ray inspection technology to quantify solder defects in BGA balls, we have conducted inspection of 3 level POP package by using a new AXI that capable of 3D-CT imaging. The new results are compared with the results of earlier AXI measurements. It is found that 3D measurements offer better defect inspection quality, lower false call and escapes.
Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard, readily available device packaging methods in which high-density packaging is achieved by: (1) using standard "packaged" memory devices, (2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads, stacked either 2-high or 4-high, and integrated into a single dual-flat-no-lead (DFN) package.
In the 1990's, both BGA (Ball Grid Array) and CSP (Chip Size Package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (Surface Mount Device) from the I 980's and THD (Through-Hole mount Device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability.
applying ink to Panel of PCB's -- Does anyone have experience of using a stainless Fine Grain SMT stencil for the purposes of applying ink to bare PCB's? We are exploring the possibility of getting a stencil to apply a letter that reflects the revision to each of 25 PCB's in a panel. We plan to utilize our MPM Momentum paste printer (we currently do it by hand) to ink these as a batch before SMT production. Basically, we would be adding to the silk screen. We are unable to have the silk changed as the customer supplies the boards, and requires the ink to reflect the current assembly revision. Basically they don't want to change their PCB revision/gerbers every time they roll their assembly revision. I am unsure if a Fine Grain Stainless SMT stencil or a different material such as a mesh stencil would be best. I tend to believe a rubber squeegee would work best, but again I am unsure. I am looking for any information or experience anyone may have.
Iron (Fe) contamination in selective solder joints -- Trying to understand the impact of iron contamination above IPC recommendations (0.02%) on selective solder joints.
Brittleness and discolouration are known but are there other factors that should be accounted for?
The following is a statement by Richard Cappetto, Senior Director, North American Government Relations at IPC, the electronics manufacturing association, on the release of the National Defense Industrial Strategy (NDIS) yesterday by the U.S. Department of Defense. A fuller statement is in this IPC Blog....
Gen3 proudly introduces the revolutionary CM Series Contaminometer, set to be available from the first quarter of 2024. This new Process Ionic Contamination Tester boasts an array of groundbreaking features designed to elevate user experience and provide unparalleled measurement capabilities....
SMTA is a non-profit international association of companies and individuals (totalling 4,000) involved in all aspects of advanced electronics assembly, surface mount and related technologies.
IPC is a US-based trade association dedicated to the competitive excellence and financial success of its nearly 2,600 member companies which represent all facets of the electronic interconnection industry, including design, printed wiring board manufacturing and electronics assembly.