Dear Abhishek, I too got the opportunity to investigate this defect Lift lead for SOT. Lead lift in IC, and SOT can occur due to various reasons. Here are some possible reasons for lead lift and ways to avoid them: During the assembly process, mechanical stress can be applied to the IC, causing the leads to lift. This stress can be a result of mishandling during the Pre reflow inspection confirm by the defect data on AOI. Thermal Stress during Soldering may be Rapid or uneven heating/cooling during the soldering process can lead to differential expansion and contraction of the IC and the PCB, leading to lead lift need to validate this behavior based on the AOI or inspection data online. since this one defect passed to the customer breaking all the Qgates this means detection needs to be re-verified at all inspection and test stations The presence of contaminants like oils, dust, FOD, or residues on the leads or the PCB pads can hinder proper solder adhesion, leading to lead lift. Material incoming Defects seem rare cases, Ensure that the coplanarity of the leads is within the specified tolerance (e.g., 100 microns) as defined in the IC datasheet. Which needs to re-confirm the program set. check the option of upgradation of the machine for co Planarity detection. Use precision machinery and inspection tools during the manufacturing process to meet the required coplanarity criteria. Implement proper quality control checks during assembly to identify and reject components with lead float outside the acceptable limits. Re-visit the PFMEA and confirm. Hope I have clarified the issue and may be helpful to you. or update your findings and action taken to learn if any new observations. regards Shrikant
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