Head in Pillow defects with memory components

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Does anyone have experience with HiP defects with DDR memory... - Dec 21, 2022 by SMTA-64304420 SMTA

HiP most of the time goes back to the component package itse... - Dec 28, 2022 by Evtimov

Look in the Express Newsletter [https://smtnet.com/express/]... - Dec 29, 2022 by davef

At SMT assembly level, the main HiP mitigation actions to co... - Jan 11, 2023 by Arnaud Grivon

SMTA-64304420

#88752

Head in Pillow defects with memory components | 21 December, 2022

Does anyone have experience with HiP defects with DDR memory components that they would be willing to share? I am interested in SMT process corrective actions and repair processes. I can discuss this privately if needed.

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Evtimov

#88767

Head in Pillow defects with memory components | 28 December, 2022

HiP most of the time goes back to the component package itself. If they are on the periphery of the part, it is a result excessive of expansion and contraction from the temperature. If it is in the middle, other contributors come in place.

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davef

#88772

Head in Pillow defects with memory components | 29 December, 2022

Look in the Express Newsletter [https://smtnet.com/express/] dated December 29, 2022 for some papers on "head in pillow"

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Arnaud Grivon

#88832

Head in Pillow defects with memory components | 11 January, 2023

At SMT assembly level, the main HiP mitigation actions to consider should be increasing the stencil thickness/aperture sizes (typically in the 4 corners where warpage is maximal) + possibly reducing the reflow peak temperature as probably indicated in the suggested papers/sources. Interested to further discuss offline, please share your email address.

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