Technical Library | 2019-06-11 09:34:37.0
Recently ACI Technologies was asked to perform failure analysis on a hermetically sealed transistor for potential electrostatic discharge (ESD) or electrostatic overstress (EOS). ACI was asked to determine if the field-failed transistor was damaged by ESD or EOS. In order to properly assess the failure, additional samples were requested.
Technical Library | 2014-04-03 18:01:13.0
A system level modeling methodology is presented and validated on a simple case. It allows precise simulations of electrostatic discharge (ESD) stress propagation on a printed circuit board (PCB). The proposed model includes the integrated circuit (IC) ESD protection network, IC package, PCB lines, passives components, and externals elements. The impact of an external component on the ESD propagation paths into an IC is demonstrated. Resulting current and voltage waveforms are analyzed to highlight the interactions between all the elements of an operating PCB. A precise measurement technique was designed and used to compare with the simulation results. The model proposed in this paper is able to predict, with good accuracy, the propagation of currents and voltages into the whole system during ESD stress. It might be used to understand why failures occur and how to fix them with the most suitable solution.
Technical Library | 1999-05-07 08:48:52.0
This paper describes how the quality and reliability of Intel's products are designed, measured, modeled, and maintained. Four main reliability topics: ESD protection, electromigration, gate oxide wearout, and the modeling and management of mechanical stresses are discussed. Based on an analysis of the reliability implications of device scaling, we show how these four topics are of prime importance to component reliability...
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