Technical Library | 2026-04-07 21:39:30.0
Field trials were conducted of wheat (Triticum aestivum) cv. Cadenza in which asparagine synthetase gene, TaASN2, had been knocked out, either on its own or together with a partial knockout of the related gene, TaASN1, using CRISPR/Cas9. Chemical mutagenesis (TILLING) TaASN2 nulls in the Claire background were also included. The main aim was to assess the free asparagine content of the grain and the conversion of free asparagine to acrylamide, a toxic contaminant, in bread, toast and biscuits. Over 2 years of trials combined, the TaASN2 and TaASN1/2 CRISPR knockouts resulted in a reduction of free asparagine in the grain of 59% and 93%, respectively, compared with Cadenza. The reduction in the TaASN2 total knockout TILLING line compared with Claire was 50%. Yield was not affected in the edited lines but was reduced in the TILLING lines. Acrylamide in bread made from a TaASN1/2 CRISPR line was below detection levels, while in a TaASN2 CRISPR line it was 14% of the Cadenza control. Even after 4min of toasting, acrylamide levels remained at 8% and 23%, respectively, of the control. The concentration in bread made from the TILLING TaASN2 knockout was 21% that for the Claire control, rising to 46% after 4min of toasting. Acrylamide in biscuits made from a TaASN1/2 CRISPR line was reduced by 93% compared with the control. The relationship between acrylamide and colour was altered in the edited and mutant lines compared with the controls, with less acrylamide forming for the same degree of colour.
Technical Library | 2018-09-21 10:12:53.0
Moisture accumulates during storage and industry practice recommends specific levels of baking to avoid delamination. This paper will discuss the use of capacitance measurements to follow the absorption and desorption behaviour of moisture. The PCB design used in this work, focused on the issue of baking out moisture trapped between copper planes. The PCB was designed with different densities of plated through holes and drilled holes in external copper planes, with capacitance sensors located on the inner layers. For trapped volumes between copper planes, the distance between holes proved to be critical in affecting the desorption rate. For fully saturated PCBs, the desorption time at elevated temperatures was observed to be in the order of hundreds of hours. Finite difference diffusion modelling was carried out for moisture desorption behaviour for plated through holes and drilled holes in copper planes. A meshed copper plane was also modelled evaluating its effectiveness for assisting moisture removal and decreasing bake times. Results also showed, that in certain circumstances, regions of the PCB under copper planes initially increase in moisture during baking.
Technical Library | 2022-09-12 14:07:47.0
Unique component handling issues can arise when an assembly factory uses highly-moisture sensitive surface mount devices (SMDs). This work describes how the distribution of moisture within the molded plastic body of a SMD is an important variable for survivability. JEDEC/IPC [1] moisture level rated packages classified as Levels 4-5a are shown to require additional handling constraints beyond the typical out-of-bag exposure time tracking. Nitrogen or desiccated cabinet containment is shown as a safe and effective means for long-term storage provided the effects of prior out-of-bag exposure conditions are taken into account. Moisture diffusion analyses coupled with experimental verification studies show that time in storage is as important a variable as floor-life exposure for highly-moisture sensitive devices. Improvements in floor-life survivability can be obtained by a handling procedure that includes cyclic storage in low humidity containment. SMDs that have exceeded their floor-life limits are analyzed for proper baking schedules. Optimized baking schedules can be adopted depending on a knowledge of the exposure conditions and the moisture sensitivity level of the device.
Technical Library | 2015-02-27 17:06:01.0
The drive towards fine pitch technology also affects the soldering processes. Selective soldering is a reliable soldering process for THT (through hole) connectors and offers a wide process window for designers. THT connectors can be soldered on the top and bottom side of boards, board in board, PCBs to metal shields or housing out of plastic or aluminum are today's state of the art. The materials that are used to make the solder connections require higher temperatures. Due to the introduction of lead-free alloys, the boards need more heat to get the barrels filled with solder. This not only affects the properties of the flux and components, but the operation temperatures of solder machines become higher (...)First the impact of temperature will be discussed for the separate process steps and for machine tooling. In the experimental part measurements are done to verify the accuracy that can be achieved using today's selective soldering machines. Dedicated tooling is designed to achieve special requirements with respect to component position accuracy.
Technical Library | 2023-07-25 16:50:02.0
Some of the new handheld communication devices offer real challenges to the paste printing process. Normally, there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils. This paper will explore a different type of step stencil for this application; a "Two-Print Stencil Process" step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005, 0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil. Design guidelines for minimum keep-out distances between the relief step, the fine pitch apertures, and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.
Technical Library | 2021-11-26 14:34:07.0
The use of desiccant bags filled with Silica Sand and or Clay beads used in conjunction with a Moisture Barrier Bag to control moisture for storage of printed circuit boards has long been an accepted practice and standard from both JEDEC and IPC organizations. Additionally, the use heated ovens for baking off moisture using the evaporation process has also been a long#2;standing practice from these organizations. This paper on alternative drying methods will be accompanied by completed independent, unbiased tests conducted by Vinny Nguyen, an engineering student (now graduated) from San Jose State University. The accompanied paper will examine the performance levels of different technologies of desiccant bags to control moisture in enclosed spaces. The tests and equipment set were reviewed by an engineer and consultant to the Lockheed Martin Aerospace Division and the IPC - TM-650 2.6.28 test method was review by engineer from pSemi. The tests were designed to mimic performance tests outlined in Mil Spec 3464, which both IPC and JEDEC have adopted for their respective standards. The test examined variables including absorption capacity rates, weight gain and release of moisture back into the enclosed area. The presentation will also address and highlight: • Similarities of PCBs and Heavy Equipment as it applies to Inspections, Causes of Failure, Types of Corrosion and Moisture Collection Points. • Performance Attributes of Different Desiccant Technologies as it applies to shape, texture, change outs, labeling and regeneration. • Venn Diagram of Electromechanical Failure with the circles 1. Current 2. Contamination 3. Humidity Presentation Available
Technical Library | 2023-07-25 16:42:54.0
Printing solder paste for very small components like .3mm pitch CSP's and 01005 Chip Components is a challenge for the printing process when other larger components like RF shields, SMT Connectors, and large chip or resistor components are also present on the PCB. The smaller components require a stencil thickness typically of 3 mils (75u) to keep the Area Ratio greater than .55 for good paste transfer efficiency. The larger components require either more solder paste height or volume, thus a stencil thickness in the range of 4 to 5 mils (100 to 125u). This paper will explore two stencil solutions to solve this dilemma. The first is a "Two Print Stencil" option where the small component apertures are printed with a thin stencil and the larger components with a thicker stencil with relief pockets for the first print. Successful prints with Keep-Outs as small as 15 mils (400u) will be demonstrated. The second solution is a stencil technology that will provide good paste transfer efficiency for Area Ratio's below .5. In this case a thicker stencil can be utilized to print all components. Paste transfer results for several different stencil types including Laser-Cut Fine Grain stainless steel, Laser-Cut stainless steel with and w/o PTFE Teflon coating, AMTX E-FAB with and w/o PTFE coating for Area Ratios ranging from .4 up to .69.
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