IC void

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Hi, can anybody give an idea how to lessen the void on a dou... - Jun 01, 2016 by slouis2014

Hello, what is the design on the stencil, that you chose? Se... - Jun 02, 2016 by Buckcho

Several important things to watch. 1. More paste can resul... - Jun 02, 2016 by Evtimov

i have tried to design the stencil as attached, but the void... - Jun 02, 2016 by slouis2014

Hi, yes have a few experiments initially i tried to increase... - Jun 02, 2016 by slouis2014

slouis2014

#75808

IC void | 1 June, 2016

Hi, can anybody give an idea how to lessen the void on a double ground pad IC. I have tried to change the stencil design, change the solder reflow setting. but i still haven't reach 75% solderability. thanks alot

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Buckcho

#75810

IC void | 2 June, 2016

Hello, what is the design on the stencil, that you chose? Send us a picture, so we can help you better.

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Evtimov

#75814

IC void | 2 June, 2016

Several important things to watch. 1. More paste can result in more voiding(I usually shoot for 50-65% coverage) 2. Make a different grid(windowpane) for you pad - try with more smaller windows 3. Try both ramp to spike or Soak profiles and see which one works better 4. change PCB design- sometimes just the design needs to be changed. How many via holes, are they buried or through holes?

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slouis2014

#75826

IC void | 2 June, 2016

i have tried to design the stencil as attached, but the void is more than 35%. do you have any idea what is the ideal diameter for the stencil aperture for the solder to spread and the flux to be released out of the component simultaneously. thanks alot.

Attachments:

Capture.JPG

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slouis2014

#75827

IC void | 2 June, 2016

Hi, yes have a few experiments initially i tried to increase the solder volume but component pin have insufficient solder. 1. The solder coverage do you calculate it by solder volume or solder area. 2. if i would achieve as you recommend 50-60 % would the result have 25% void. 3. I have already redesign the PCB with window pane, the result is good but i am worried about the contact area between the component and the PCB pad. 4. change the soak time to 6-10 secs. 5. i already cover the via hole, so it would not be a problem. Someone mentioned that there is an ideal stencil aperture diameter that will provide lower void rate, do you have any idea about it. thanks alot for the help.

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