No HDL Knowledge Needed; IPs Slash Design Time; Get it Right the First Time Through Power & Digital Management Simulation
With PAC-Designer 6.0, designers can use a simple, easy to learn, push-button design methodology to implement designs into the FPGA portion of the Platform Manager devices. Three new IP cores, which provide correct-by-construction application solutions, have also been announced.
Simultaneously, Lattice is announcing the new ispLEVER® 8.1 SP1 Starter software, which also supports the digital design portion of Platform Manager devices. This capability can be used for more complex digital designs targeted to the FPGA section of the Platform Manager device.
“PAC-Designer software’s point and click, intuitive, error-free syntax LogiBuilder utility has revolutionized power management design methodology for integrating various power management functions into a single chip,” said Gordon Hands, Director of Marketing for Lattice Low density and Mixed Signal Solutions. “Now this same design methodology can also be used to integrate digital board management functions into the Platform Manager’s FPGA.”
Platform manager devices provide programmable analog, CPLD and FPGA blocks to integrate a circuit board’s power management and digital management functions. The PAC-Designer 6.0 software provides a GUI-based design methodology for analog engineers using intuitive dialog boxes to configure analog sections; the LogiBuilder design methodology to integrate power management functions into the on-chip CPLD; and the LogiBuilder or VHDL or Verilog design methodology to integrate digital board management functions into the FPGA section of the Platform Manager devices. The PAC-Designer 6.0 software also provides three free correct-by-construction IP cores to implement functions such as closed-loop margining with Voltage ID (VID) Support, I2C/SPI slave interface and non-volatile fault logging into external SPI memory. Digital designers can also use ispLEVER 8.1 software to integrate other board management functions into the on-chip FPGA section using standard digital design methods.
Pricing and Availability
Lattice's PAC-Designer software and companion ispLEVER Starter for Windows are available now for free download from the Lattice website, http://www.latticesemi.com/pac-designer
IP cores and reference designs are available from the Lattice website at http://www.latticesemi.com/products/intellectualproperty
About the New Lattice Platform Manager Family
The Platform Manager product family consists of two devices, the LPTM10-1247 and LPTM10-12107. The LPTM10-1247 device can monitor 12 voltage rails and supports 47 combined digital inputs and digital outputs, while the LPTM10-12107 monitors up to 12 voltage rails and supports 107 combined digital inputs and digital outputs. Functionally, these devices include both a power management section and a digital board management section. The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies. The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O.
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit http://www.latticesemi.com