HILLSBORO, OR - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of a comprehensive video display interfaces suite for High-Definition Multimedia Interface (HDMI 1.3a), Digital Visual Interface (DVI), and 7:1 LVDS Interface. All of these display interfaces are available as free Reference Designs for the award winning, mid-range LatticeECP3™, while selected free Reference Designs can also be ported to the LatticeECP2M™ and LatticeXP2™ FPGA families. The silicon-proven Reference Designs will empower embedded, digital signage, and industrial customers to design high-performance entertainment, information and vision systems. The programmable FPGA- based solutions also enable customers to quickly implement proprietary image processing functions that will help differentiate their products.
Lattice is targeting all display market segments with comprehensive solutions for three popular multimedia standards. The HDMI solution is useful for processing high-definition, non- copy protected audio-visual signals from network servers, industrial cameras, and other sources to projectors and other video displays. The DVI solution is particularly useful for digital signage, consumer and industrial customers who require only video and no audio for their application and are sensitive to any additional royalty costs. The 7:1 LVDS solution is excellent for transferring large amounts of video data from board to board within an electronic system (embedded applications).
The silicon-proven Reference Designs implement the Physical Layer Functions for three popular video standards for reliable and efficient serial transmission. The first Reference Design, HDMI Physical Interface, leverages the LatticeECP3 SERDES and its associated PLL to automatically detect the HDMI resolution. This allows a design to use fewer components and enables quicker time to market because no processor firmware needs to be written. Further cost saving is achieved as the discrete PHY is removed and integrated into the LatticeECP3 device.
The second Reference Design, DVI Physical Interface, encodes/decodes and serializes/de-serializes video data on the low power embedded SERDES in LatticeECP3 FPGAs using the Transition Minimized Differential Signaling mechanism. It can both transmit and receive DVI video data.
The third Reference Design, 7:1 LVDS Physical Interface, is implemented on the 1Gbps LVDS-capable source synchronous differential I/Os. This Reference Design leverages unique pre-engineered I/O components in newer Lattice FPGA families, such as high-speed LVDS buffers, DDR registers, precision PLLs and built-in gearbox logic, to optimally manage the data rates. The embedded applications also frequently require image and video processing before or after the transmission. Lattice's low-cost, mid-range FPGAs enable designers to build integrated devices with both processing and efficient data transmission functionalities.
“We are pleased to offer our customers a comprehensive suite of video display interfaces for developing advanced and high performance video display applications,” said Shakeel Peera, Director of Marketing for High Density Solutions at Lattice Semiconductor. “Lattice is committed to providing a comprehensive silicon ecosystem that includes evaluation kits, reference designs, software tools and IP cores so our customers can accelerate their time to market.”
For more information on Video Display solutions from Lattice Semiconductor, please visit http://www.latticesemi.com/video. Free Reference Designs and associated documentation also can be downloaded from the Lattice website.
About the LatticeECP3 FPGA Family
The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 users I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireline and wireless infrastructure applications.
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. or more information, visit http://www.latticesemi.com