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SMTA Announces 7th International Wafer-Level Packaging Conference (IWLPC) Program

Jun 28, 2010

Minneapolis, MN - The SMTA and Chip Scale Review magazine are pleased to announce the presentation line-up for the 7th Annual International Wafer-Level Packaging Conference. The IWLPC will be held October 11-14, 2010 at the Santa Clara Marriott Hotel in Santa Clara, California. Registration is now available on-line. Early Bird conference pricing is in effect until September 10, 2010, after which registration prices will go up $100.

Attendees will benefit by gaining the latest knowledge with six application-oriented tutorials, expert panel discussions, a presentation from distinguished keynote speaker Dr. Bradley McCredie from IBM, and 15 tech sessions.

The conference will include three tracks with papers covering:

  • Wafer Level Packaging

  • MEMS Packaging

  • 3-D Integration

Exhibit space is limited but there are still tabletop spaces available. Please contact Leslee Johns, leslee@smta.org, at SMTA with questions or for more information about the exhibition.

This premier industry event explores leading-edge design, material, and process technologies focused on Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer level packaging solutions for integration, cost, and performance requirements.

Visit http://www.iwlpc.com for more information.

Contact Melissa Serres at 952-920-7682 or melissa@smta.org with questions.

The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

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