Design For Test (DFT) Training

Feb 04, 2010



Monday, April 19 to Wednesday, April 21, 2010

11400 Cronridge Drive, Suite H, Owings Mills, Maryland, 21117, USA

The Test Connection, Inc. (TTCI) will host a 3 day DFT training course. In this seminar you will learn all aspects of Design for Testability, from what it is, why you might need it, why someone would object to it, and what it can and cannot accomplish. You will learn how today's technology has become elusive to certain failure modes and how important it is to expose them through more testable designs. First you will learn some simple techniques to enhance observability and controllability. You will learn how you can access hundreds of internal points with as few as four additional edge connector pins. You will learn specific guidelines for both digital and analog circuit testability. You will learn structured testability techniques, such as internal and boundary-scan. You will come away with a deep understanding of the IEEE 1149.1 (JTAG) standard's operation, use and even its limitations. You will also learn some new techniques in testability, including IDDQ testing and I/O Mapping. In the second part of the course, you will learn what built-in [self] test (BIST) is and how it can be specified. You will learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators. With these building blocks you will be able to evaluate a number of BIST architectures. You will learn BIT Software techniques (sometime called modeling) and consider the effect false alarms have on BIT. You will finally be able to specify BIT for your products and look at the possibilities of BIT taking over some of the ATE functions.

If you would like to see more on the topics, please check out our website; There is a button that you can ‘click’ that will list all of the topics we are looking to cover or contact Bert Horner on the phone: 410-526-2800 or email:

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