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International Wafer-Level Packaging Conference (IWLPC) Best of Conference Paper and Plans for 2010 Announced

Dec 17, 2009

Minneapolis, MN - The SMTA and Chip Scale Review magazine are pleased to announce the Best of Conference Paper from the 6th Annual International Wafer-Level Packaging Conference and Exhibition, which was held October 27-30, 2009 at the Marriott Hotel in Santa Clara, California. After review by members of the 2009 IWLPC Technical Committee, In-Soo Kang (NEPES Corporation) has been selected as the Best of Conference award winner for his technical paper on "Development of Wafer Level Package of Normal and High Pin Count Devices for Mobile Applications."

The paper was selected based on the following criteria:

  • Technical paper must be provided (if speaker submitted an abstract only he/she does not qualify)

  • Must be original work - rehash of previously reported work does not qualify

  • Must include data - data can include application, design rules / modeling, technical data including mechanical dimensions for test vehicles, design of experiments matrix, assembly or reliability data.

  • Work must be pertinent to the industry, IWLPC and SMTA objectives

The paper can be found on the conference proceedings, and is available for purchase in the SMTA BookStore on-line at http://www.smta.org/store/book_store.cfm.

Plans are underway for the 2010 conference. Lee Smith, Amkor Technology, will act as technical Chair. Ken Gilleo, ET-Trends LLC, will be the General Chair. New members of the technical committee are Francoise von Trapp, 3D Incites, and Ron Edgar, Chip Scale Review.

Sponsored jointly by the SMTA and Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages.

For more information contact Melissa Serres Marx at 952-920-7682 or melissa@smta.org.

Visit http://www.iwlpc.com to view the full program and watch for a complete event review.

The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

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