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SMT, PCB Electronics Industry News

News from Everett Charles Technologies


Everett Charles Technologies’ Jason Mroczkowski to Present at IWLPC 2009

Oct 01, 2009

Everett Charles Technologies announces that Jason Mroczkowski, RF Engineering and Product Management, will hold a presentation titled “Signal Integrity Simulation of the Wafer Test Environment” at the upcoming International Wafer-Level Packaging Conference and Tabletop Exhibition, scheduled to take place October 27-30, 2009 at the Santa Clara Marriott in Santa Clara, CA. The presentation will be held during Session 16, “WLP Reliability and Test,” which is scheduled to take place Friday, October 30, 2009 from 3-5 p.m.

The Wafer Test industry is very competitive with short time to market and low cost being the major driving forces. Today there is an option available to help ensure performance of wafer test hardware prior to manufacturing, thus minimizing time to market and cost of test. That option is signal integrity simulation. Simulation provides confidence that the electrical performance of the test environment matches the requirements of the device under test, before fabrication. Simulation also eliminates extensive lab testing and allows a direct path from fabrication to production.

This presentation will provide a description of a full test interface path and discuss the simulation techniques used to capture each structure within that path. Most importantly, Mroczkowski will discuss the structures and interfaces that must be captured in simulation to ensure the results match actual measurements. Additionally, he will discuss optimization and the multiple areas of focus. One of the challenges is to determine which optimization will have the largest impact on performance. Finally, Mroczkowski will conclude by showing an example simulation including a device model, package model, wafer probe model, and PCB layout model all within one simulation environment. He will explain how simulation and optimization methods previously described are used to meet device requirements for a specific wafer test application.

Everett Charles Technologies, Inc., a subsidiary of the Dover Corporation (NYSE: DOV), is a leading manufacturer of electrical test products and services, including semiconductor test products, bare-board automatic test systems, Pogo test contacts, and bare and loaded PCB test fixtures. ECT manufacturing, service, and support facilities are ISO registered with locations throughout the United States, Europe, and Asia. The company has been awarded numerous patents and participates actively in developing industry standards. Corporate offices for Everett Charles Technologies are located at 700 E. Harrison Ave., Pomona, California 91767. Additional information about ECT is available via the Internet at http://www.ectinfo.com.

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