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International Wafer-Level Packaging Conference (IWLPC) Features Five Half-Day Tutorials

Aug 07, 2009

Minneapolis, MN – The SMTA and Chip Scale Review magazine are pleased to announce five half-day tutorials for the 6th Annual International Wafer-Level Packaging Conference. The IWLPC will be held October 27-30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, California.

The IWLPC tutorials are application oriented and structured to combine field experience with scientific research to solve everyday problems. They are offered on Tuesday, October 27 and Wednesday, October 28, preceding the technical conference.

Tutorial topics and presenters include Advanced Packaging Technologies and Future Interconnection Trends, Joseph Fjelstad, Verdant Electronics; Nanoelectronics, MEMS, and MOEMS - Products & Packages, Ken Gilleo, Ph.D., ET Trends LLC; Design for Wafer Level CSP Technology, Vern Solberg, Solberg Technical Consulting; Advanced Flip Chip Technology and Processing, Dan Baldwin, Ph.D., Engent, Inc., and 3D Packaging Applications, Requirements, Infrastructure and Technologies, Lee Smith, Amkor Technology.

Sponsored jointly by the SMTA and Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages. The event is sponsored by Dow Electronic Materials, NEXX Systems, Pac Tech USA, and Technic, Inc.

For more information on the IWLPC contact Melissa Serres Marx at 952-920-7682 or melissa@smta.org.

Visit http://www.iwlpc.com to view the full program and to register.

The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

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