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International Wafer-Level Packaging Conference (IWLPC) Program Finalized and On-line Registration Now Open

Jul 24, 2009

Minneapolis, MN – The SMTA and Chip Scale Review magazine are pleased to announce the presentation line-up for the 6th Annual International Wafer-Level Packaging Conference. The IWLPC will be held October 27-30, 2009 at the Santa Clara Marriott Hotel in Santa Clara, California. Registration is now being processed on-line. Early Bird conference pricing is in effect until September 25th, 2009, after which registration prices will go up $100.

"With 5 great tutorials, expert panel discussions, distinguished keynote speaker Dr. Rao Tummala, and 18 tech sessions featuring a new track on MEMS WL and WLP, this program will be one of the best sources for information on WLP, CSP, and 3D packaging this year." said Conference General Chair Dr. Ken Gilleo, ET-Trends LLC.

Sponsored jointly by the SMTA and Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages. The event is sponsored by Dow Electronic Materials, Pac Tech USA, and Technic, Inc.

For more information on the IWLPC contact Melissa Serres Marx at 952-920-7682 or melissa@smta.org.

Visit http://www.iwlpc.com to view the full program and to register.

The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

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