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International Wafer-Level Packaging Conference Issues Call for Papers

Jan 23, 2008

San Jose, CA - �The International Wafer-Level Packaging Conference (IWLPC) has issued a call for papers for its fifth annual program on Oct. 13-16 at the Wyndham Hotel in San Jose.

The IWLPC features a wide variety of subjects within the areas of wafer-level-, chip-scale- and 3D/stacked packaging. Complementary papers in test are also being sought. A new addition to the conference is the inclusion of presentations on photovoltaic packaging and processing.

Abstracts of potential papers should be about 200 words. The deadline is March 3. Abstracts may be submitted online at http://www.iwlpc.com or by e-mail to melissa@smta.org.

The conference will feature three tracks over the Oct. 15-16 two-day period. The two prior days are devoted to professional workshops. A few of the specific topics within wafer-level packaging are MEMS wafer-level packaging, lithography options, wafer-surface cleaning, metrology, lead-free technologies and plasma treatments.

Stacked package/3D topics will include mixed-chip assembly issues, wafer bonding, wafer thinning, package substrates and interposers and SIP versus SOC formats.

The IWLPC is co-presented by /Chip Scale Review/ magazine and the SMTA.

The SMTA is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

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