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International Wafer-Level Packaging Conference (IWLPC) Call for Papers

Apr 07, 2015

SMTA and Chip Scale Review magazine are pleased to announce plans for the 12th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. This premier industry event explores leading-edge design, material, and process technologies being applied to Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer level packaging solutions for integration, cost, and performance requirements.

The conference includes three tracks with two days of technical paper presentations covering Wafer Level Packaging, 3-D (Stacked) Packaging, and MEMS Packaging. If you would like to present at this conference, please submit a 200-300 word abstract by April 17, 2015. Please include a title, author name, and contact information with your abstract. Technical papers are required and will be due August 21, 2015.

For more information, please contact Patti Coles at 952-920-7682 or patti@smta.org.

IWLPC will return to the DoubleTree Hotel in San Jose, California from October 13-15, 2015. Visit http://www.iwlpc.com/ for more information.

The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

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