SMT, PCB Electronics Industry News

SMT, PCB Electronics Industry News

News from JTAG Technologies B. V.


Preview for ITC for JTAG Technologies for ITC 2014, 21 -23 October, Washington State Convention Center, Seattle

Oct 21, 2014

JTAG Technologies BV (Eindhoven, The Netherlands), a vendor of test and debug tools based on boundary-scan, will showcase the following JTAGLive products as well as new system upgrades in Hall 1, booth 606:

Support for new IEEE JTAG Standard (IEEE P1687) – New Demo – Revolutionary Extension to Basic IEEE 1149.1

Newly available as an addition to our standard range of tools, is a module aimed at the support of new IEEE P1687 (aka IJTAG – Internal JTAG) compliant devices.  IJTAG/P1687 has been devised as an evolutionary extension to the basic IEEE 1149.1 and IEEE 1500 standards and describes how embedded (test) instruments within a device or S-O-C may be accessed using the conventional 4/5 wire JTAG port.

While the instruments themselves (typically HS-IO modules for high-speed interface testing like DDR3 etc.) are not described as part of the standard all the mechanisms for interacting with the instruments are. JTAG Technologies has therefore developed tools to read in the new P1687 description format and make available the features of all compliant devices to our customers.

The specific P1687 module supports the key language elements of the proposed standard, namely:- ICL- Instrument Connectivity Language that defines the hardware/logic interface to the instruments IP and; PDL – Procedural Description Language (a close relative of TCL) that defines the patterns or vectors that are applied and sensed via the logic interfaces in order to invoke the instruments’ IP functions. Our P1687 tool contains all the necessary parsers and interpreters required to create working applications for P1687 compatible devices that are now emerging in some key industry sectors.

JTAGLive CoreCommander -

CoreCommander is a simple, low-cost system that uses microprocessor core emulation
modes to aid hardware validation and board (PCBA) testing. The easy user interface and low-cost
JTAG interface hardware will enable users to construct read and write sequences from the processor
core to embedded or external peripherals and peripheral controllers in minutes. Python support further enables users to construct more sophisticated test sequences using CoreCommander Python libraries as required  - all from within the user-friendly JTAGLive environment. Supported Cores include ARM 7/9/11, Cortex, Marvell PXA, Microchip PIC32, TI C2000, Freescale PowerPC/Nexus, and Infineon TriCore.

CoreCommander routines are ideal for diagnosing faults on ‘dead-kernel’ boards in either design debug or repair, since no on-board code is required to set memory reads and writes. Boundary-scan deficient parts can also be better utilised during production test, as CoreCommander-driven functions increase fault coverage. Since CoreCommander is Python-based it complements perfectly the JTAGLive Script product, allowing access to mixed-signal parts such as ADCs and DACs and also synchronised testing to full boundary-scan devices.

The solutions take control of key processor core functions using the built-in emulation/debug functions of the ‘processor core and are designed by test engineers for use by test engineers. JTAG CoreCommander uses dual modes of operation, namely ‘Interactive’ or ‘Python embedded’.

More Features – the new JTAG CoreCommander checks-out the FPGA Zone

CoreCommander for FPGAs is a generic solution based on VHDL code that allows engineers to bridge from the standard JTAG test and programming port (TAP) to proprietary IP cores (e.g. DDR controllers, E-net MAC, USB controllers etc..) and harness them for test purposes.

The base of CoreCommander for FPGAs is a RTL coded translator block that provides access to proprietary IP cores through commonly implemented bus structures such as ‘Wishbone’, AMBA, Avalon and CoreConnect. This translator block can either be permanently or temporarily programmed into a gate–array. Linker software provided with the module automatically links the translator block with IP blocks and the FPGA specific interface layer to build the complete file set that may be programmed in the FPGA. Access to the translator is subsequently provided by a Python (JFT) library module.


JTAG Live is the economic easy-to-use family of board debug tool JTAG Technologies. Products within the family include Buzz, AutoBuzz, Clip and Script. For more information please visit www.jtaglive.com

JTAG Technologies is a market leader and technology innovator of boundary-scan software and hardware products and services. The company was the first to bring to the market such important advances as automated test generation, automated fault coverage analysis, automated flash and PLD programming via boundary-scan, and visualized boundary-scan analysis. Its customers include world leaders in electronics design and manufacturing such as Ericsson, Flextronics, Honeywell, Medtronic, Motorola, Nokia, Philips, Raytheon, Rockwell-Collins, Samsung, and Sony. Its innovative boundary-scan products provide test preparation, test execution, test result analysis and in-system programming applications. With an installed base of over 7000 systems worldwide, JTAG Technologies serves the communications, medical electronics, avionics, defence, automotive, and consumer industries with offices throughout North America, Europe and Asia. JTAG Technologies headquarters are located in Eindhoven, The Netherlands. For more information please visit www.jtag.com

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Preview for ITC for JTAG Technologies for ITC 2014, 21 -23 October, Washington State Convention Center, Seattle news release has been viewed 658 times

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