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International Wafer-Level Packaging Conference (IWLPC) Program Finalized and Registration Now Open

Aug 02, 2012

The SMTA and Chip Scale Review magazine are pleased to announce the presentation line-up for the 9th Annual International Wafer-Level Packaging Conference.  The IWLPC will be held November 5-8, 2012 at the DoubleTree by Hilton Hotel in San Jose, California.  Registration is now available on-line and Early Bird conference pricing is in effect until October 5, 2012, after which registration prices will go up $100.

The conference includes three tracks with two days of technical paper presentations covering: Wafer Level Packaging; 3-D (Stacked) Packaging; and MEMS Packaging.  Attendees will benefit by gaining the latest knowledge from eight application-oriented tutorials, 10 technical sessions, expert panel discussions on MEMS and 3D Integration, and a keynote presentation from John Ellis, bestselling author of 'Dormant Curse,' titled "A Trojan Chip in Your Smartphone? It's Coming..."

The Wafer Level Packaging track sessions will include presentations dealing with Fan-Out, Embedded Wafer-Level Packaging, Materials, Reliability, Testing and other WLP-related topics.  Presenters come from Deca Technologies, DETEK, Dow Corning Corporation, Dynaloy, Interconnect Devices, Inc., NANIUM, S.A., NuSil Technology, Sekisui Chemical Co., Ltd., STATS ChipPAC Ltd, and STMicroelectronics.

Papers in the 3D track sessions will cover recent findings on Thin Wafer Handling (TWH), Bonding, Processes, Through Silicon Vias (TSV), and other 3D packaging issues.  Presenters come from a variety of major companies including AGC, Daetec LCC, EV Group, Inc., Imec VZW, Invensas, Inc., Matech, Nordson ASYMTEK, SEMATECH, SoftMEMS, STATS ChipPAC Ltd., Tokyo Electron Europe Ltd, and Ultratech Inc.

Papers from the MEMS track sessions will cover Co-Design Strategies, Yield and Strength of MEMS Device Sealing, Sealing Dispensing for MEMS Wafer Capping, Bonding and Contacting of Vertically Integrated 3-D Microscanners, MEMS Hermeticity and Reliability Testing, and Reliability of TSVs and Wafer-Level Bonding for a 3D integrable SOI Based MEMS Application.

The MEMS Integration Strategies Panel Discussion will examine the issue from a packaging perspective.  Roger Grace, Roger Grace Associates, will moderate the panel consisting of experts Mary Ann Maher, SoftMEMS, Sean Ding, Ph.D., MEMSIC, and Maik Wiemer, Ph.D., Fraunhofer Institute.

The Panel Discussion on 3D Integration will answer the questions: how did we get here and where do we need to go now?  Keith Cooper, SET North America, will moderate the expert panel consisting of Jeff Calvert, Dow Chemical, John Lau, Ph.D., Industrial Technology Research Institute (ITRI), David Love, Oracle, Garret Oakes, EV Group, Peter Ramm, Fraunhofer EMFT, and Tom Strothmann, STATS ChipPAC.

Exhibit space is limited but there are still tabletop spaces available. Please contact Seana Wall,, at SMTA or any sales representative with Chip Scale Review at with questions or for more information about the exhibition.

This premier industry event explores leading-edge design, material, and process technologies focused on Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer-level packaging solutions for integration, cost, and performance requirements.

Visit for more information.
Contact Patti Hvidhyld at 952-920-7682 or with questions.

The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

Chip Scale Review, now entering its 15th year, is the leading international magazine serving the semiconductor, IC and electronic device packaging market.


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