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  • International Wafer-Level Packaging Conference (IWLPC) Concludes Successfully

International Wafer-Level Packaging Conference (IWLPC) Concludes Successfully

Nov 08, 2011

The SMTA and Chip Scale Review magazine are pleased to announce the 8th Annual International Wafer-Level Packaging Conference and Exhibition was a resounding success.  The IWLPC was held October 3-6, 2011 at the Santa Clara Marriott Hotel in Santa Clara, California.  Attendees enjoyed presentations from 40+ speakers covering three tracks: wafer-level packaging, 3D packaging, and MEMS packaging.  Attendance was up 30% from last year.

The exhibit hall was busy in between sessions and breaks displaying their technology. The table top displays included presentations with products or services focused on the TSV, Wafer Level and Packaging technology.

The conference opened Wednesday morning with a presentation by Matt Nowak from Qualcomm tilted "High Density TSV Chip Stacking". The presentation focused on the opportunities, purpose, challenges and momentum with this technology. Matt spoke on the advantages of TSV including Performance Enhancement, Improved Efficiency, Form Factor Miniaturization, and Cost Reduction.

In the afternoon session, a six member panel of industry experts was formed to discuss the infrastructure issues for technology adoption of TSV.  Simon McElrea, Invensas Corporation, Tessera Technologies, Inc., moderated the discussion.  Panelists included Jim Walker, Gartner Technology; Ron Leckie, INFRASTRUCTURE Advisors; Jan Vardaman, TechSearch International; Peter Ramm Ph.D., Fraunhofer EMFT; Sesh Ramaswami, Applied Materials, Inc.; and Andre Rouzaud Ph.D., CEA-Leti.  Each panel member discussed their opinions on the TSV evolution process.

Wednesday evening concluded with a Keynote Dinner and Address.  Raj Master, Microsoft, provided a very interesting look at "Thermal and Power considerations in Consumer Electronics."

Thursday morning kicked off with a Plenary Session led by John Lau, Industrial Technology Research Institute.  He presented "Evolution, Challenge, and Outlook of 3D Si/IC Integrations."

The Thursday afternoon Panel Discussion titled "Will 2.5D and 3D Compete or Coexist?" was also notable.  Panelists included Scott Jewler, Powertech Technology; Ron Huemoller, Amkor Technology; Phil Marcoux, PPM Associates; and Rao Tummala. Ph.D, 3D Systems Packaging Research Center.

Sponsored jointly by the SMTA and Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level, 3D/stacked, and MEMS packaging.  The event was sponsored by Amkor Technology, EV Group, NEXX Systems, NANIUM, Pac Tech USA, STATS ChipPAC, and SUSS MicroTek, and supported by MEPTEC and Yole Développment.

Plans are now underway for the 2012 event.  Visit http://www.iwlpc.com to view the full program and watch for a complete event review.  Contact Patti Hvidhyld at 952-920-7682 or patti@smta.org with questions.


The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

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