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International Wafer-Level Packaging Conference (IWLPC) Offers In-Depth Tutorials

Aug 15, 2011

The SMTA and Chip Scale Review magazine are pleased to announce eight in-depth tutorials will be offered at IWLPC 2011.  Tutorials are application-oriented and structured to combine field experience with scientific research to solve everyday problems. The IWLPC will be held October 3-6, 2011 at the Santa Clara Marriott Hotel in Santa Clara, California.

IWLPC 2011 Tutorial Topics Include:

  • Achieving High Reliability of Lead-Free Soldering - Materials Consideration
  • Primer for the Design and Fabrication of Silicon Interposers
  • TSV and Key Enabling Technologies for 3D IC/Si Integration and WLP
  • MEMS Packaging and Reliability
  • Wafer Level Packaging
  • Chip Scale & Embedded Chip Packaging
  • IC Package Cost Reduction Using Supply Chain Modeling
  • Advanced Flip Chip Technology and Processing

This premier industry event explores leading-edge design, material, and process technologies focused on Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer-level packaging solutions for integration, cost, and performance requirements.

Contact Patti Hvidhyld at 952-920-7682 or patti@smta.org with questions.


The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

Chip Scale Review, now entering its 15th year, is the leading international magazine serving the semiconductor, IC and electronic device packaging market.

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