May 28, 2003
WHO:
Cadence Design Systems, Inc. (NYSE: CDN)
WHEN:
June 2-4, 2003
WHERE:
Anaheim Convention Center
WHAT:
Cadence Vertical Solution for PCI Express
Customers will learn about a vertical solution that addresses their PCI Express needs. The demonstration will show how companies can leverage Cadence SoC design expertise, tools and IP to be first-to-volume with PCI Express solutions. It will feature the Cadence Incisive verification platform, PureSpec IP (demonstrating compliance and interoperability) from Denali and the Cadence PCI Express semiconductor IP solution.
NOTE:
This demo also will be shown at the PCI-SIG Developers Conference June 2 and 3 at the San Jose Convention Center.
Specification-driven design flow for Custom ICs
This demonstration shows the flow from Virtuoso(R) Schematic Composer and Cadence(R) Analog Design Environment to Aptivia circuit design environment, with a focus on importing legacy and work-in-process designs. Customers will see how the specification controls many simulations in parallel in order to fully characterize a design, and how an engineering change can be accounted for. Customers will learn how to detect a failure and analyze the results, and demonstrate the team design concepts. The demo includes a look at the comparison and creation of analog behavioral models (Verilog-A) from transistor design by automatically creating a characterization plan.
Featured products:Aptivia Circuit Design Environment and Aptivia Design Characterization Modeling (DCM)
Physical verification & analysis
Customers will see the latest developments in Assura physical verification, the leader in analog and M/S (SoC) verification. Integrated with the Cadence Analog Design Environment, Assura provides a superior physical verification solution for custom analog and M/S designs. Assura is the first physical verification solution to provide "abstract" verification, a new approach that signals new possibilities in addressing physical verification challenges.
Featured products:Assura Design Rule Checker (DRC), Assura Layout Versus Schematic Verifier (LVS), Assura Parasitic Extractor (RCX)
Custom chip authoring
This demonstration focuses on the benefits of Virtuoso Chip Editor--the cockpit for chip finishing, featuring OpenAccess infrastructure technology for high-performance and high-capacity interactive editing, abstract swapping, PG text creation, layer fill using Assura physical verification. Blocks authored in the Virtuoso-XL layout environment will be combined with digital blocks from the Cadence SoC Encounter environment to create a M/S custom IC. Customers will see new connectivity-aware layout features that allow precise, manual, geometric editing while assuring design integrity from automatic tools. Pre/post-route creation, editing with the new wire editor, and top-level MS auto routing with Cadence Chip Assembly Router will also be shown.
Featured products:Virtuoso Chip Editor
RTL Compiler - Synthesis for timing closure
This demonstration shows the next-generation optimization technology from Get2Chip, which was recently acquired by Cadence. Cadence RTL Compiler produces a higher-quality netlist to speed the design closure process. See how RTL Compiler works with existing design flows to increase chip performance and decrease design times.
Featured products: Cadence RTL Compiler
Nanometer sign-off analysis and finishing
The demo focuses on the key design steps after design implementation and prior to tapeout. Customers will learn about the Encounter digital IC design platform and its silicon-proven nanometer sign-off analysis flow covering 3-D extraction, IR drop, timing, and crosstalk analysis. The demo includes how to migrate from the Encounter platform to OpenAccess seamlessly for chip finishing and wire editing.
Featured products: SoC Encounter RTL-to-GDSII Hierarchical IC Implementation Solution, Fire & Ice(R) QX C Extractor, CeltIC(TM) Crosstalk Analyzer, SignalStorm(TM) Signal Integrity Timing Solution, VoltageStorm(TM) SoC Power Grid Verification, Virtuoso Chip Editor
SoC Encounter - Hierarchical RTL-to-GDSII solution
Cadence SoC Encounter offers a complete, integrated RTL-to-GDSII hierarchical IC implementation solution for nanometer designs. This demo emphasizes the importance of a wires-first, continuous convergence methodology, along with the speed, capacity, and integrated design environment of the Encounter platform. Designed specifically to handle 10+ million gates flat and 50+ million gates hierarchically, SoC Encounter produces realizable designs fast--without compromising quality.
Featured products: Cadence SoC Encounter RTL-to-GDSII Hierarchical IC Implementation Solution
Unified Methodology for Fast & Efficient Verification
The functional verification of nanometer-scale ICs requires speed and efficiency. Yet today's fragmented methodologies make it impossible to optimize either. Each verification stage has its own methodology, tools, models, and user interface. Engineers must re-create almost everything at every stage. This demo shows how the Incisive(TM) functional verification platform enables a unified verification methodology that delivers the fastest, most efficient verification in the industry, from system design to system design-in for all design domains.
Featured products: Incisive unified simulator, Incisive-XLD, Incisive-XLD Base, Incisive-AMS, Incisive-SPW, NC-VHDL, NC-Verilog, NC-SystemC, and Palladium(R) accelerator/emulator.
OpenAccess: A Common API for Open Interoperability
OpenAccess is a community-managed, open-source API and reference implementation created as an interoperability platform for nanometer design. It provides a high-performance, high-capacity C++ API and database engineered for fast development. This demo shows how Cadence is leveraging the power of this infrastructure technology to deliver significant performance and capacity improvement for layout editing using Virtuoso Layout Editor.
Featured Product: Virtuoso Layout Editor running side-by-side on OpenAccess and CDBA
Interconnect design and analysis across silicon-package-board
Customers will see how SPECCTRAQuest(R) ST expert can be used for the exploration, design, optimization and implementation of multigigabit interconnect from IC die through IC package onto the PCB. SPECCTRAQuest offers a single integrated pre- and post-route design solution for SI/crosstalk and power integrity. This is the only solution that enables the optimization of the interconnect from I/O cell to I/O cell across the fabrics of silicon, IC package and PCB.
Featured products: SPECCTRAQuest SI expert
High-speed constraint-driven PCB Design
Today's PCB systems designers face the incredible challenge of managing design performance from IC die to IC die. Designers must manage timing paths and budgets across multiple fabrics concurrently in order to meet system performance goals. This demo shows why most systems companies today use a Cadence PCB design flow, the industries only high-speed constraint driven silicon-package-board solution.
Featured products: Concept(R) HDL, Allegro(R) PCB Layout, SPECCTRA(R) Router, SPECCTRAQuest high-speed PCB design and analysis, Constraint Manager(TM)
IC Package design and analysis
The Cadence IC Packaging solution provides an advanced environment for the complete design and analysis of advanced IC packages including stacked die systems in package (SiP). Customers will see how it offers the industry's most robust set of capabilities by providing the framework for IC integration, physical layout, package modeling, interconnect routing, and analysis which are all key in developing an optimized IC device.
Featured products: Advanced Package Designer, Advanced Package Engineer (includes SPECCTRAQuest for IC Packaging)
For additional information about Cadence at DAC visit dac.cadence.com.
For more information, please contact:
Judy Erkanat
Cadence Design Systems, Inc.
408-894-2302 direct
408-515-0939 cell
Karin Gilles
The Hoffman Agency
408-975-3038 direct
408-806-0416 cell
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