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Technical Articles From Universal Instruments Corporation

Read technical articles about electronics manufacturing added by Universal Instruments Corporation


13 technical articles added by Universal Instruments Corporation

Company Information:

Universal Instruments Corporation

Universal Instruments is a global leader in the design and manufacture of advanced automation and assembly equipment solutions for the electronics manufacturing industry.

Conklin, New York, USA

Manufacturer of Assembly Equipment, Pick and Place

  • Phone +1-800-432-2607
  • Fax +1-607-779-4466

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(3) products in the catalog

(13) technical library articles

(58) news releases

Solder Joint Reliability Under Realistic Service Conditions

Oct 30, 2014 | P. Borgesen, S. Hamasha, M. Obaidat, V. Raghavan, X. Dai; Department of Systems Science & Industrial Engineering, Binghamton University, M. Meilunas, M. Anselm; Universal Instruments Corporation.

The ultimate life of a microelectronics component is often limited by failure of a solder joint due to crack growth through the laminate under a contact pad (cratering), through the intermetallic bond to the pad, or through the solder itself. Whatever the failure mode proper assessments or even relative comparisons of life in service are not possible based on accelerated testing with fixed amplitudes, or random vibration testing, alone. Effects of thermal cycling enhanced precipitate coarsening on the deformation properties can be accounted for by microstructurally adaptive constitutive relations, but separate effects on the rate of recrystallization lead to a break-down in common damage accumulation laws such as Miner's rule. Isothermal cycling of individual solder joints revealed additional effects of amplitude variations on the deformation properties that cannot currently be accounted for directly.

We propose a practical modification to Miner's rule for solder failure to circumvent this problem. Testing of individual solder pads, eliminating effects of the solder properties, still showed variations in cycling amplitude to systematically reduce subsequent acceleration factors for solder pad cratering. General trends, anticipated consequences and remaining research needs are discussed...

Testing Intermetallic Fragility on Enig upon Addition of Limitless Cu

Jan 23, 2014 | Martin K. Anselm, Ph.D. and Brian Roggeman Universal Instruments Corp.

As reliability requirements increase, especially for defense and aerospace applications, the need to characterize components used in electronic assembly also increases. OEM and EMS companies look to perform characterizations as early as possible in the process to be able to limit quality related issues and improve both assembly yields and ultimate device reliability. In terms of BGA devices, higher stress conditions, RoHS compatible materials and increased package densities tend to cause premature failures in intermetallic layers. Therefore it is necessary to have a quantitative and qualitative test methodology to address these interfaces....

Process Issues For Fine Pitch CSP Rework and Scavenging

Mar 04, 2013 | Anthony A. Primavera Ph.D.

Chip-scale (or chip-size) packages are rapidly becoming an important element in electronics due to their size, performance, and cost advantages [Hou, 1998]. The Chip Scale Package (CSP) is becoming a key semiconductor package type, particularly for consumer products. Due to their relatively smaller size, new challenges are presented in the rework and repair of CSPs. (...) The specific focus of this paper is the removal process for rework of CSPs and the site scavenging methods required to properly prepare the circuit board for a new component. Process factors such as the heating, fluxing and, atmosphere are discussed....

Optimizing Flip Chip Substrate Layout for Assembly

Nov 29, 2007 | Pericles Kondos, Peter Borgesen, Dan Blass, and Antonio Prats.

Programs have been developed to predict the expected yield of flip chip assemblies, based on substrate design and the statistics of actual manufactured boards, as well as placement machine accuracy, variations in bump sizes, and possible substrate warpage. These predictions and the trends they reveal can be used to direct changes in design so that defect levels will fall below the acceptable limits. Shapes of joints are calculated analytically, or when this is not possible, numerically by means of a public domain program called Surface Evolver. The method is illustrated with an example involving the substrate for a flip chip BGA....

The Pin-in-Paste (or AART) Process for Odd Form and Through Hole Printed Circuit Boards

Sep 27, 2007 | Jay B. Hinerman, DEK Inc; K. Srihari, Ph.D., Department of Systems Science and Industrial Engineering State University of New York; George R. Westby, Director - SMT Laboratory, Universal Instruments Corporation.

Considerable interest exists in the process known as the pinin- paste, or the Alternative Assembly and Reflow Technology (AART) process. The AART process allows for the simultaneous reflow of both odd-form and through hole devices as well as surface mount components. This process has several advantages over the typical mixed technology process sequence that includes wave soldering and/or hand soldering, often in addition to reflow soldering....

Achieving SMT Compatible Flip Chip Assembly With No-Flow Fluxing Underfills

Aug 09, 2007 | Tony DeBarros and Doug Katze of Emerson and Cuming And Pericles Kondos of Universal Instruments

Recent developments in No Flow-Fluxing Underfill (NFFUF) products have demonstrated their utility to enhance the reliability of flip chip assemblies with reduced processing steps over conventional capillary flow methods. This basic work considered processing conditions such as dispensed volume and placement force, speed and dwell time. Further evaluations of these new products on a variety of flip chip assembly configurations manufactured by various processes have been undertaken to provide further evidence of their suitability and potential in high volume electronic manufacturing. This paper summarizes the recent evaluations and discusses new studies of additional assembly configurations, which include higher input/output (l/O) counts up to full arrays in excess of 1200 l/Os....

Low Force Placement Solution For Delicate and Low IO Flip Chip Assemblies

Jun 27, 2007 | Jason Higgins - Universal Instruments Corporation, Robert Hemann - Medtronic Microelectronics Center.

Traditionally most flip chips were designed with large bumps on a coarse pitch. However, as the trend towards smaller, more compact assemblies continues the sizes of semiconductor packages are forced to stay in line. New designs are incorporating smaller bump diameters on increasingly aggressive pitches, and in many cases decreasing the total IO count. With fewer and smaller bumps to distribute the load of the placement force it is becoming increasingly vital for equipment manufacturers to meet the challenge in offering low force placement solutions. One such solution will be presented in the following discussion. Also presented will be ways to minimize the initial impact spike that flip chips experience upon placement....

Lead-free and Tin-lead Assembly and Reliability of Fine-pitch Wafer-Level CSPs

May 31, 2007 | Michael Meilunas, Muffadal Mukadam, Peter Borgesen, Hari Srihari

This paper discusses solder paste printing and flux dipping assembly processes for 0.4 and 0.5mm pitch lead-free WLCSPs and the corresponding assembly results and thermal cyclic reliability obtained. Variables evaluated include reflow ambient, paste type, and stencil design. Reliability is also compared to results for the same components assembled under identical conditions using SnPb solder....

The Proximity of Microvias to PTHs And Its Impact On The Reliability

May 09, 2007 | Anthony Primavera Manager - CSP Consortium Universal Instruments Corporation, Jaydutt Joshi, Package Development Engineer - Conexant Systems Inc.

High Density Interconnect (HDI) technology is fast becoming the enabling technology for the next generation of small portable electronic communication devices. These methods employ many different dielectrics and via fabrication technologies. In this research, the effect of the proximity of microvias to Plated Through Holes (PTHs) and its effect on the reliability of the microvias was extensively evaluated. The reliability of microvia interconnect structures was evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing (-55oC to +125oC). Comprehensive failure analysis was performed on microvias fabricated using different via fabrication technologies....

Fragility of Pb-free Solder Joints

Apr 18, 2007 | Universal Instruments Corporation

Recent investigations have revealed that Pb-free solder joints may be fragile, prone to premature interfacial failure particularly under shock loading, as initially formed or tend to become so under moderate thermal aging. Depending on the solder pad surface finish, different mechanisms are clearly involved, but none of the commonly used surface finishes appear to be consistently immune to embrittlement processes. This is of obvious concern for products facing relatively high operating temperatures for protracted times and/or mechanical shock or strong vibrations in service....

Effects of Assebly Process Variables on Voiding at a Thermal Interface.

Apr 04, 2007 | Muffadal Mukadam, Jeff Schake, Peter Borgesen, Krishnaswami Srihari.

The present work offers a discussion and a first case study to identify and illustrate voiding mechanisms for a particular TIM between a heat spreader and the back of a flip chip. Pronounced differences were observed between stencil printing and dispensing in terms of initial void formation, apparently related to the specific properties of the material. Measurements of the effects of heat ramp rate and peak temperature showed the subsequent evolution and final void size distribution to be determined by the initial part of the cure profile up to the material gelling temperature....

Lead-free Rework Process For Chip Scale Packages

Mar 28, 2007 | Arun Gowda and K. Srihari, Ph.D. - Electronics Manufacturing Research and Services, Anthony Primavera, Ph.D. Consortium Manager - Universal Instruments Corporation

Legislation against the use of lead in electronics has been the driving force behind the use of lead-free solders, surface finishes, and component lead finishes. The major concern in using lead-free solders in the assembly and rework Chip Scale Packages (CSPs) is the relatively high temperatures that the components and the boards experience. Fine-pitch CSPs have very low standoff heights following assembly making inspection and rework of these components more difficult. One other concern pertinent to rework is the temperature of the neighboring components during rework. These issues, coupled with the limitations of rework equipment to handle lead-free reflow temperatures, make the task of reworking lead-free assemblies more challenging....

Assembly And Reliability Issues Associated With Leadless Chip Scale Packages

Oct 02, 2006 | Michael Meilunas of Universal Instruments Corporation, Binghamton, NY; Muffadal Mukadam, and Hari Srihari of Binghamton University, Binghamton, NY

This paper addresses the assembly and reliability of 0.5 mm pitch leadless Chip Scale Packages (CSP) on .062" immersion Ag plated printed circuit boards (PCB) using Pb-free solder paste. Four different leadless CSP designs were studied and each was evaluated using multiple PCB attachment pad designs....

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