Jun 10, 2010 | Mike Bixenman, Steve Stach
This paper researches the effectiveness of the R.O.S.E. cleanliness testing process for dissolving and measuring ionic contaminants from boards soldered with no-clean and lead-free flux technologies....
Publisher: Kyzen Corporation
Jun 03, 2010 | Thomas McCarthy, Sean Reynolds, Jon Skelly
Strategies for successful design and manufacture of microwave multilayer printed circuit boards. All aspects from pad registration, dimensional stability, impedance fluctuation, fusion bonding, thermal ageing, z-axis expansion, reliability, to Young's mod...
May 27, 2010 | Randy Kong, Cheryl Tulkoff, Craig Hillman (presented at: SMTA China East Conference 2010)
The quad flat pack no lead or quad flat non-leaded (QFN) is one of the fastest growing package types in the electronics industry today. While the advantages of QFNs are well documented, concerns arise with its reliability and manufacturability. Acceptance of this package, especially in long-life, severe-environment, high-reliability applications, is currently limited. One of the most common drivers for reliability failures is inappropriate adoption of new technologies, such as the case with QFN. In this presentation, we will review and discuss QFN related reliability concerns and challenges, and propose Physics-of-Failure (PoF) based approaches to allow the confident introduction of QFN components into electronics products....
Publisher: DfR Solutions
DfR Solutions has world-renowned expertise in applying the science of Reliability Physics to electrical and electronics technologies, and is a leading provider of quality, reliability, and durability (QRD) research and consulting for the electronics industry.
College Park, Maryland, United States
May 24, 2010 | Bernd Hauptmann – Sales Manager Seica Deutschland GmbH
Die echte Integration zwischen ATE Flying Prober und Boundary Scan Tester, vorgestellt von Seica, kombiniert das Beste von beiden Testtechniken und multipliziert die Vorteile für den Anwender....
Publisher: SEICA SpA
May 20, 2010 | James Stanbridge, Steve Lees
As several industry pundits have expressed in recent years: "the era of 'one test method fits all' seems well behind us." For most test managers with even a modest mix of products, trying to formulate a test policy/philosophy has become a tricky balancing act at the best of times. James Stanbridge, Sales Manager UK for JTAG Technologies, and Steve Lees Managing Director of ATE Solutions look at the options....
Publisher: JTAG Technologies B. V.
May 12, 2010 | Ronald C. Lasky, Ph.D., PE; Indium Corporation of America Daryl Santos, Ph.D., Aniket A. Bhave; Binghamton University
Numerous studies have shown that greater than 60% of end of line defects in SMT assembly can be traced to solder paste and the printing process. Reflowing adds another 15% or so. In light of this fact, it is surprising that no simplified procedure for solder paste evaluation has been documented. This paper is about such a procedure....
Publisher: Indium Corporation
May 06, 2010 | Dr. Rita Mohanty; Speedline Technologies, Rajiv L. Iyer, Daryl Santos; Binghamton University
Stencil printing technology has come a long way since the early 80’s when SMT process gained importance in the electronics packaging industry. In those early days, components were fairly large, making the board design and printing process relatively simple. The current trend in product miniaturization has led to smaller and more complex board designs. This has resulted into designs with maximum area utilization of the board space. It is not uncommon, especially for hand held devices, to find components only a few millimeters from the edge of the board. The board clamping systems used in the printing process have become a significant area of concern based on the current board design trend....
Publisher: Speedline Technologies, Inc.
Speedline Technologies serves the electronics assembly and semiconductor packaging industries with class-leading equipment, responsive support and unparalleled process knowledge.
Franklin, Massachusetts, United States
Apr 29, 2010 | Jianbiao Pan, Tzu-Chien Chou, Jasbir Bath, Dennis Willie, Brian J. Toleno
The purpose of this paper is to investigate the effects of reflow time, reflow peak temperature, thermal shock and thermal aging on the intermetallic compound (IMC) thickness for Sn3.0Ag0.5Cu (SAC305) soldered joints....
Publisher: Flextronics International
Apr 22, 2010 | Ronald C. Lasky, Ph.D., PE, Professor Daryl Santos, Ph.D., Joseph R. Cloyd
It is now widely accepted that using designed experiments is the most effective way to optimize surface mount technology (SMT) processes. This situation begs the question "what is an effective strategy in implementing this powerful tool?" This paper will present such a strategy that incorporates Taguchi's approach for screening, full factorial analysis for optimization and central composite design for precise modeling. We will present these techniques using MINITABTM Release 13 statistical software and printed circuit board industry applications....
Publisher: Indium Corporation
Apr 22, 2010 | Subrat Prajapati
Current situation: Present Rejection = 18%.
Sigma Level = 2.42
Scope of Project: Vendor PCB Assembly to Functional Testing of PCBA...