Apr 28, 2016 | Julien Perraud, Arnaud Grivon.
Underfilling is a long-standing process issued from the micro-electronics that can enhance the robustness and the reliability of first or second-level interconnects for a variety of electronic applications. Its usage is currently spreading across the industry fueled by the decreasing reliability margins induced by the miniaturization and interconnect pitch reduction. (...)
This paper will address the control of surface mount under filled assemblies, focusing on applicable inspection techniques and possible options to overcome their limitations....
Apr 21, 2016 | David Geiger, Georgie Thein; AEG, Flextronics International Inc.
The world of electronics continues to increase functional densities on products. One of the ways to increase density of a product is to utilize more of the 3 dimensional spaces available. Traditional printed circuit boards utilize the x/y plane and many miniaturization techniques apply to the x/y space savings, such as smaller components, finer pitches, and closer component to component distances.
This paper will explore the evolution of 3D assembly techniques, starting from flexible circuit technology, cavity assembly, embedded technology, 3 dimensional surface mount assembly, etc....
Publisher: Flex (Flextronics International)
Apr 14, 2016 | Louis Y. Ungar
A system level test, usually built-in test (BIT), determines that one or more subsystems are faulty. These subsystems sent to the depot or factory repair facility, called units under test (UUTs) often pass that test, an event we call No-Fault-Found (NFF). With more-and more electronics monitored by BIT, it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA), cannot duplicate (CNDs)or retest OK (RTOK) events. NFFs at the depot are caused by FAs, CNDs, RTOKs as well as a number of other complications. Attempting to repair NFF scan waste precious resources, compromise confidence in the product, create customer dissatisfaction, and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action at the system level are invalid. NFFs can be caused by real failures or may be a result of system level false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs.
This paper will shed some light on this trade-off. Finally, we will explore approaches for dealing with the NFF issue in a cost effective manner....
Publisher: A.T.E. Solutions, Inc.
The leading Test, ATE and Testability consulting and educational firm, offering various test related courses. Maintains the BestTest Directory, a test community knowledge base. Publishes The BestTest eNewsletter.
Los Angeles, California, USA
Apr 08, 2016 | Julian Coates
PCB assembly designs become more complex year-on-year, yet early-stage form/fit compliance verification of all designed-in components to the intended manufacturing processes remains a challenge. So long as librarians at the design and manufacturing levels continue to maintain their own local standards for component representation, there is no common representation in the design-to-manufacturing phase of the product lifecycle that can provide the basis for transfer of manufacturing process rules to the design level. A comprehensive methodology must be implemented for all component types, not just the minority which happen to conform to formal packaging standards, to successfully left-shift assembly and test DFM analysis to the design level and thus compress NPI cycle times.(...)
This paper will demonstrate the technological components of the working solution: the logic for deriving repeatable and standardized package and pin classifications from a common source of component physical-model content, the method for associating DFA and DFT rules to those classifications, and the transfer of those rules to separate DFM and NPI analysis tools elsewhere in the design-through-manufacturing chain resulting in a consistent DFM process across multiple design and manufacturing organizations....
Publisher: Mentor Graphics
Mar 31, 2016 | Vladimir Kraz
Electrical overstress causes damage to sensitive components, including latent damage. A significant source of EOS is high-frequency noise in automated manufacturing equipment. This paper analyses sources of such noise, how it affects components and how to mitigate this problem....
Publisher: OnFILTER, Inc.
Mar 25, 2016 | Margaret Bishop (CAMI Research)
Ready to purchase a new tester? Interested in improving productivity & quality? Ask these technical questions of your potential supplier....
Publisher: CAMI Research Inc.
CableEye® continuity and HiPot pass/fail & diagnostic Cable & Harness Test Systems w simple scripting, labeling, documentation, cataloging & relay control. Dynamically display continuity, Ω, diodes, IR, dielectric breakdown & more
Acton, Massachusetts, USA
Mar 24, 2016 | Karl Sauter; Oracle Corporation, Joe Smetana; Alcatel-Lucent
Today's Electronic Industry is changing at a high pace. The root causes are manifold. So world population is growing up to eight billions and gives new challenges in terms of urbanization, mobility and connectivity. Consequently, there will raise up a lot of new business models for the electronic industry. Connectivity will take a large influence on our lives. Concepts like Industry 4.0, internet of things, M2M communication, smart homes or communication in or to cars are growing up. All these applications are based on the same demanding requirement – a high amount of data and increased data transfer rate. These arguments bring up large challenges to the Printed Circuit Board (PCB) design and manufacturing.
This paper investigates the impact of different PCB manufacturing technologies and their relation to their high frequency behavior. In the course of the paper a brief overview of PCB manufacturing capabilities is be presented. Moreover, signal losses in terms of frequency, design, manufacturing processes, and substrate materials are investigated. The aim of this paper is, to develop a concept to use materials in combination with optimized PCB manufacturing processes, which allows a significant reduction of losses and increased signal quality....
Mar 17, 2016 | Michael L. Cieslinski, Brent A. Fischthal
The rapid growth of electronic devices across the globe is driving manufacturers to enhance high-speed mass production techniques in the PCB assembly arena. As manufacturers drive to reduce costs while maximizing production by expanding facilities, updating automation equipment, or implementing lean six sigma techniques, the potential to build scrap product or rework printed circuit boards increases dramatically.
Manufacturers have two general paths to reduce the costs of high-speed printed circuit board assembly production. The first path is to reduce cost by focusing on high quality printing and mounting. The other, increasingly popular option is to utilize low-cost materials. In either case, the baseline must provide a consistent high-speed solder paste printing method, which considers the fill, snap-off, and cleaning processes.
Building on our expertise and testing, this paper will highlight the two trains of thought with specific focus on how low-cost materials affect print performance. It will also explore technologies, which can help provide stable, high-speed screen printing....
PFSA develops and supports innovative manufacturing automation equipment, processes and solutions around the core of electronic assembly, microelectronic, software and circuit manufacturing
Rolling Meadows, Illinois, USA
Mar 10, 2016 | Kris Troxel, Aileen Allen, Elizabeth Elias Benedetto, Rahul Joshi
Since the implementation of the European Union RoHS directive in 2006, the electronics industry has seen an expansion of available low-silver lead (Pb)-free1 alloys for wave soldering, miniwave rework, BGA and CSP solder balls, and, more recently, solder pastes for mass reflow. The risks associated with the higher processing temperatures of these low-silver (Ag between 0-3 wt%) solder alloys, such as potential laminate or component damage, increased copper dissolution, and reduced thermal process windows may present manufacturing challenges and possible field reliability risks for original equipment manufacturers (OEMs). In order to take advantage of potential cost reduction opportunities afforded by these new alloys, while mitigating manufacturing and reliability risks, the company has defined test protocols [1-4] that can be used for assessing new Sn-Ag-Cu(SAC), Sn-Ag, and Sn-Cu alloys for general use in electronics.
This paper describes initial test results for low-silver alloys using these solder paste alloy assessment protocols for BGAs and leaded components, and the impact of the alloys on printed circuit assembly process windows....
Publisher: HP Inc.
Mar 03, 2016 | David Ciufo, Sujatha Ramanujan, Janet Heyen, Michael Carmody; Intrinsiq Materials, Sunny Patel; Candor Industries.
This paper discusses a nano copper based paste for use in via filling. The company manufactures nano copper and disperses the coated nano copper into a paste in combination with micron copper. The resultant paste is injected or fills a via. The via is subsequently sintered by means of photonic sintering, or by heat in a reducing environment. The process will be accomplished in under an hour and results in filled solid copper vias....
Publisher: Intrinsiq Materials Inc.