Apr 04, 2013 | Todd L Kolmodin, VP Quality
This paper will outline and define what requirements must be adhered to for the OEM community to truly achieve the IPC class product from the Electrical Test standpoint. This will include the test point optimization matrix, Isolation (shorts) parameters and Continuity (opens) parameters. This paper will also address the IPC Class III/A additional requirements for Aerospace and Military Avionics. The disconnect exists between OEMs understanding the requirements of their specific IPC class design versus the signature that will be presented from their design. This results in many Class III builds failing at Electrical Test... First published in the 2012 IPC APEX EXPO technical conference proceedings...
Publisher: Gardien Services USA
Apr 03, 2013 | Don Fitchett
PLC vs PAC Difference & PAC Automation Controller Defined: This PLC vs PAC Difference article defines the PAC automation controller in relationship to the PLC. A PLC vs PAC comparison. Even more importantly, this article explains in great detail the need to differentiate when it comes to requesting and delivering PAC and/or PLC training....
Publisher: Business Industrial Network
Offers training software and videos. Also on site training and seminars that qualify for CEUs to maintenance, engineering and management professionals.
St. Louis, Missouri, USA
Mar 28, 2013 | Alexander Ippich
For the last couple of years, the main concerns regarding the electrical performance of blank PCB boards were impedance and ohmic resistance. Just recently, the need to reduce insertion loss came up in discussions with blank board customers (...) The paper describes the test vehicle and the testing methodology and discusses in detail the electrical performance characteristics. The influence of the independent variables on the performance characteristics is presented. Finally the thermal reliability of the boards built applying different copper foils and oxide replacements was investigated....
Publisher: Multek Inc.
Mar 27, 2013 | Allen Duck
Vapor phase, once cast to the annals’ of history is making a comeback. Why? Reflow technology is well developed and has served the industry for many years, it is simple and it is consistent. All points are true – when dealing with the centre section of the bell curve. Today’s PCB manufacturers are faced with many designs which no longer fall into that polite category but rather test the process engineering groups with heavier and larger panels, large ground planes located in tricky places, component mass densities which are poorly distributed, ever changing Pb Free alloys and higher process temperatures. All the time the costs for the panels increase, availability of “process trial” boards diminishes and yields are expected to be extremely high with zero scrap rates. The final process in the assembly line has the capacity to secure all the value of the assembly or destroy it. If a panel is poorly soldered due to poor Oven setup or incorrect programming of the profile the recovery of the panel is at best expensive, at worst a loss. For these challenges people are turning to Vapor Phase....
Publisher: A-Tek Systems Group LLC
Distributor of the highest quality SMT assembly equipment. Our 45 years of combined experience and commitment to excellence have earned us the reputation as the premier distributor in the Americas.
Longmont, Colorado, USA
Mar 21, 2013 | C.P. Hunt, O. Thomas, D. Di Maio, E. Kamara, H. Lu
This paper explores the behaviour of a copper test vehicle with multiple reflowed solder joints, which has direct relevance to ball grid arrays (BGA) and high density interconnect structures. The paper explores the relative stress conditions on the distributed joints and the sensitivity to ball joint shape... First published in the 2012 IPC APEX EXPO technical conference proceedings...
Publisher: National Physical Laboratory
Mar 14, 2013 | Reza Ghaffarian, Ph.D.
Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings....
Publisher: Jet Propulsion Laboratory
Mar 12, 2013 | David Lober and Mike Bixenman, D.B.A.
High density and miniaturized circuit assemblies challenge the solder paste printing process. The use of small components such as 0201, 01005 and μBGA devices require good paste release to prevent solder paste bridging and misalignment. When placing these miniaturized components, taller paste deposits are often required. To improve solder paste deposition, a nano-coating is applied to laser cut stencils to improve transfer efficiency. One concern is the compatibility of the nano-coating with cleaning agents used in understencil wipe and stencil cleaning. The purpose of this research is to test the chemical compatibility of common cleaning agents used in understencil wipe and stencil cleaning processes.Compatibility of Cleaning Agents With Nano-Coated Stencils...
Publisher: KYZEN Corporation
Mar 07, 2013 | Michael Matthews, Ken Holcomb, Jim Haley, Catherine Shearer
The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings...
Publisher: Ormet Circuits, Inc.
Manufacturer of sintering, electrically conductive materials. Applications include semiconductor die attach, component attach, via fill, z-axis interconnection, conductive lines and traces and plated-through hole fill.
San Diego, California, USA
Mar 07, 2013 | Pete Doyon, VP of Product Management
No one can deny that organizations across the country have been greatly affected by the decline in the economy. The manufacturing industry is no different. Even now as things seem to be looking up, companies are continually looking to cut costs and increase efficiencies. In addition, these companies must remain compliant with the strict quality and safety standards of the industry, adding even more pressure. Because of this, innovative, automated and easy to use products are needed more than ever before to help companies achieve their goals....
Publisher: Schleuniger, Inc.
Mar 04, 2013 | Anthony A. Primavera Ph.D.
Chip-scale (or chip-size) packages are rapidly becoming an important element in electronics due to their size, performance, and cost advantages [Hou, 1998]. The Chip Scale Package (CSP) is becoming a key semiconductor package type, particularly for consumer products. Due to their relatively smaller size, new challenges are presented in the rework and repair of CSPs. (...) The specific focus of this paper is the removal process for rework of CSPs and the site scavenging methods required to properly prepare the circuit board for a new component. Process factors such as the heating, fluxing and, atmosphere are discussed....
Publisher: Universal Instruments Corporation