Electronics Manufacturing Technical Articles
Papers and articles related to SMT, PCB & EMS industry.
- Technical Library
840 SMT / PCB Assembly Related Technical Articles
Jul 13, 2017 | K. Tellefsen, M. Holtzer, T. Cucu, M. Liberatore, M. Schmidt - Alpha Assembly Solutions, S. Moser, L. Henneken, P. Eckold, U. Welzel, R. Fritsch, D. Schlenker - Robert Bosch GmbH
Controlled humidity and temperature controlled surface insulation resistance (SIR) measurements of flux covered test vehicles, subject to a direct current (D.C.) bias voltage are recognized by a number of global standards organizations as the preferred method to determine if no clean solder paste and wave soldering flux residues are suitable for reliable electronic assemblies. The IPC, Japanese Industry Standard (JIS), Deutsches Institut fur Normung (DIN) and International Electrical Commission (IEC) all have industry reviewed standards using similar variations of this measurement. (...)
This study will compare the results from testing two solder pastes using the IPC-J-STD-004B, IPC TM-650 188.8.131.52 surface insulation resistance test, and IPC TM-650 2.3.25 in an attempt to investigate the correlation of ROSE methods as predictors of electronic assembly electrical reliability....
Publisher: Alpha Assembly Solutions
Jul 06, 2017 | Zhenyu Zhao1, Chuan Chen, Yuming Wang, Lei Liu, Guisheng Zou, Jian Cai and Qian Wang - Tsinghua University, Chang Yong Park - Samsung Electronics
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments....
Publisher: Samsung Electronics
Jun 29, 2017 | Glenn Oliver, Jonathan Weldon - DuPont, Chudy Nwachukwu - Isola, John Coonrod - Rogers Corporation, John Andresakis - Park Electrochemical, David L. Wynants, Sr. - Taconic Advanced Dielectric Division
Currently there is no industry standard test method for measuring dielectric properties of circuit board materials at frequencies greater than about 10 GHz. Various materials vendors and test labs take different approaches to determine these properties. It is common for these different approaches to yield varying values of key properties like permittivity and loss tangent. The D-24C Task Group of IPC has developed this round robin program to assess these various methods from the "bottom up" to determine if standardized methods can be agreed upon to provide the industry with more accurate and valid characteristics of dielectrics used in high-frequency and high-speed applications....
Jun 29, 2017 | Tuan Tran
What's the most cost-effective method for testing prototype PCBs? Should the assembler do it, or the client's in-house engineers? This article explains all....
Publisher: Power Design Services
Jun 23, 2017 | Tuan Tran
End-to-end PCB assembly by world-class companies like Power Design Services allows you to focus on your core competencies with the added benefits of reduced cost and time to market. From material procurement to circuit board design and manufacturing, and supply chain management, we serve your needs helping you reach customers faster. Here is an overview of what our turnkey electronic manufacturing services consist of, and how you can use them to reduce your build time and cost....
Publisher: Power Design Services
Defect Features Detected by Acoustic Emission for Flip-Chip CGA/FCBGA/PBGA/FPBGA Packages and Assemblies
Jun 22, 2017 | Reza Ghaffarian, Ph.D.
C-mode scanning acoustic microscopy (C-SAM) is a non-destructive inspection technique showing the internal features of a specimen by ultrasound. The C-SAM is the preferred method for finding “air gaps” such as delamination, cracks, voids, and porosity. This paper presents evaluations performed on various advanced packages/assemblies especially flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. For comparison, representative x-ray images of the assemblies were also gathered to show key defect detection features of the two non-destructive techniques....
Publisher: Jet Propulsion Laboratory
Nondestructive Inspection of Underfill Layers Stacked up in Ceramics-Organics-Ceramics Packages with Scanning Acoustic Tomography (SAT)
Jun 15, 2017 | Justin Zeng, Francoise Sarrazin, Jie Lian, Ph.D., Zhen (Jane) Feng, Ph.D., Lea Su, Dennis Willie, David Geiger - Flex International Inc., Masafumi Takada, Natsuki Sugaya - Hitachi Power Solutions, George Tint, Ph.D. - HDI Solutions
Ceramics packages are being used in the electronics industry to operate the devices in harsh environments. In this paper we report a study on acoustic imaging technology for nondestructively inspecting underfill layers connecting organic interposers sandwiched between two ceramics substrates.
First, we inspected the samples with transmission mode of scanning acoustic tomography (SAT) system, an inspection routine usually employed in assembly lines because of its simpler interpretation criteria: flawed region blocks the acoustic wave and appears darker. In this multilayer sample, this approach does not offer the crucial information at which layer of underfill has flaws. To resolve this issue, we use C-Mode Scanning in reflection mode to image layer by layer utilizing ultrasound frequencies from 15MHz to 120MHz. Although the sample is thick and contains at least 5 internal material interfaces, we are able to identify defective underfill layer interfaces....
Publisher: Flex (Flextronics International)
Jun 14, 2017 | Tuan Tran
Flexible circuitry may be preferable to rigid circuitry in situations where space or weight is limited....
Publisher: Power Design Services
Jun 13, 2017 | Louis Zakraysek
For tin-rich solder alloys, 200 C (392 F) is an extreme temperature. Intermetallic growth in tin-copper systems is known to occur and is believed to bear a direct relationship to failure mechanisms. This study of morphological changes with time at elevated temperatures was made to determine growth rates of tin-copper intermetallics. Preferred growth directions, rates of thickening, and notable changes in morphology were observed.
Each of four tin-base alloys was flowed on copper and exposed to temperatures between 100 C and 200 C for time periods of up to 32 days. Metallographic sections were taken and the intermetallics were examined. Intermetallic layer thickening is characterized by several distinct stages. The initial growth of side plates is extremely rapid and exaggerated. This is followed by retrogression (spheroidization) of the elongated peaks and by general thick-...
Publisher: General Electric
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Jun 13, 2017 | Chris Anglin
The advent of miniaturized electronics for mobile phones and other portable devices has required the assembly of smaller and smaller components. Currently 01005 passives and 0.3 mm CSPs are some of the components that must be assembled to enable these portable electronic devices. It is widely accepted that about 65% of all end of the line defects occur in the stencil printing process. Given all of the above, it is critical that a precision stencil printing process be developed to support miniaturized electronic assembly.
This paper is a summary of a significant amount of experimental data and process optimization techniques that were employed to establish a precision SMT printing process....
Publisher: Indium Corporation