
First published in the 2012 IPC APEX EXPO technical conference proceedings
by: Anthony J. Suto, Teradyne Inc.
Increased pressures to reduce time to market and time to volume have forced many manufacturers of populated printed circuit boards to rely on capacitively coupled, un-powered, vectorless in-circuit test techniques to identify open pins on ICs and connectors. Unfortunately, faster signals and higher-density printed circuit boards (PCBs) have placed pressures on designers to reduce the number of test pads that provide electrical access for vectorless test techniques.
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