With a broad technology portfolio ranging from leadframe and laminate packages to advanced fan-out and fan-in wafer level technology, flip chip interconnect, System-in-Package (SiP), Through Silicon Via (TSV) and 2.5D/3D packaging, STATS ChipPAC provides customers with innovative and cost-effective semiconductor solutions. STATS ChipPAC differentiates itself through innovative packaging solutions in embedded Wafer Level Ball Grid Array (eWLB), encapsulated Wafer Level Chip Scale Packaging (eWLCSP) and fcCuBE® technology as well as our breakthrough wafer level manufacturing method known as FlexLineTM.
Founded in Singapore in 1994, STATS ChipPAC grew successfully over the years into a global Outsourced Semiconductor Assembly and Test (OSAT) provider with strategic manufacturing operations in Singapore, South Korea and China. These sites are integrated with our global network of research and development, design and customer support offices throughout Asia, the United States and Europe.
STATS ChipPAC Inc Postings
Jan 17, 2018 | Nokibul Islam, Vinayak Pandey, KyungOe Kim
Fine pitch copper (Cu) Pillar bump has been growing adoption in high performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities, thus assembling such packages using a standard mass reflow (MR) process and maintaining its performance is a real and serious challenge. (...)
In this study a comprehensive finding on the assembly challenges, package design, and reliability data will be published.
Originally published in the SMTA International 2016...